| Message ID | 20240802070951.1086616-1-wenst@chromium.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: mediatek: mt8195: Correct clock order for dp_intf* | expand |
On Fri, Aug 02, 2024 at 03:09:50PM +0800, Chen-Yu Tsai wrote: > The clocks for dp_intf* device nodes are given in the wrong order, > causing the binding validation to fail. > > Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes") > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Thanks, Nícolas
On 02/08/2024 09:09, Chen-Yu Tsai wrote: > The clocks for dp_intf* device nodes are given in the wrong order, > causing the binding validation to fail. > > Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes") > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 989e8ac545ac..e89ba384c4aa 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -3252,10 +3252,10 @@ dp_intf0: dp-intf@1c015000 { > compatible = "mediatek,mt8195-dp-intf"; > reg = <0 0x1c015000 0 0x1000>; > interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; > - clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, > - <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, > + clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, > + <&vdosys0 CLK_VDO0_DP_INTF0>, > <&apmixedsys CLK_APMIXED_TVDPLL1>; > - clock-names = "engine", "pixel", "pll"; > + clock-names = "pixel", "engine", "pll"; > status = "disabled"; > }; > > @@ -3522,10 +3522,10 @@ dp_intf1: dp-intf@1c113000 { > reg = <0 0x1c113000 0 0x1000>; > interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; > power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > - clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, > - <&vdosys1 CLK_VDO1_DPINTF>, > + clocks = <&vdosys1 CLK_VDO1_DPINTF>, > + <&vdosys1 CLK_VDO1_DP_INTF0_MM>, > <&apmixedsys CLK_APMIXED_TVDPLL2>; > - clock-names = "engine", "pixel", "pll"; > + clock-names = "pixel", "engine", "pll"; > status = "disabled"; > }; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 989e8ac545ac..e89ba384c4aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3252,10 +3252,10 @@ dp_intf0: dp-intf@1c015000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c015000 0 0x1000>; interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, - <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&vdosys0 CLK_VDO0_DP_INTF0>, <&apmixedsys CLK_APMIXED_TVDPLL1>; - clock-names = "engine", "pixel", "pll"; + clock-names = "pixel", "engine", "pll"; status = "disabled"; }; @@ -3522,10 +3522,10 @@ dp_intf1: dp-intf@1c113000 { reg = <0 0x1c113000 0 0x1000>; interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, - <&vdosys1 CLK_VDO1_DPINTF>, + clocks = <&vdosys1 CLK_VDO1_DPINTF>, + <&vdosys1 CLK_VDO1_DP_INTF0_MM>, <&apmixedsys CLK_APMIXED_TVDPLL2>; - clock-names = "engine", "pixel", "pll"; + clock-names = "pixel", "engine", "pll"; status = "disabled"; };
The clocks for dp_intf* device nodes are given in the wrong order, causing the binding validation to fail. Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)