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Lin" , , , , , , , Alexandre Mergnat CC: Bear Wang , Pablo Sun , Macpaul Lin , Sen Chu , Chris-qj chen , MediaTek Chromebook Upstream , Chen-Yu Tsai Subject: [PATCH v3 2/5] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs Date: Fri, 27 Sep 2024 14:50:38 +0800 Message-ID: <20240927065041.15247-2-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240927065041.15247-1-macpaul.lin@mediatek.com> References: <20240927065041.15247-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240926_235050_817578_2E757B6E X-CRM114-Status: GOOD ( 13.27 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due to an excessively long 'interrupts' property. The error message was: infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long To address this issue, update the compatbile matching rule for 'interrupts' property. This change allows flexibility in the number of interrupts for new SoCs like MT8195. The purpose of these 5 interrupts is also added into description. Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema") Signed-off-by: Macpaul Lin --- .../bindings/iommu/mediatek,iommu.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) Changes for v2: - commit message: re-formatting and add a description of adding 5 interrupts. - add 'description' and 'maxItems: 5' for 'interrupt' property of 'mt8195-iommu-infra' - others keeps 'maxItems: 1' Changes for v3: - Refine the description for 'interrupts' property and fixes the compatible matching rules. - Refine commit message. diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ea6b0f5f24de..10e2bb0f0704 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -96,7 +96,13 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + description: | + Usually, the IOMMU requires only 1 interrupt. + + The IOMMU of MT8195 has 5 banks: 0/1/2/3/4. + Each bank has a set of APB registers corresponding to the + normal world, protected world 1/2/3, and secure world, respectively. + Therefore, 5 interrupt numbers are needed for MT8195. clocks: items: @@ -210,6 +216,23 @@ allOf: required: - mediatek,larbs + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-iommu-infra + + then: + properties: + interrupts: + maxItems: 5 + + else: + properties: + interrupts: + maxItems: 1 + additionalProperties: false examples: