| Message ID | 20241209134459.27110-6-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | net: dsa: Add Airoha AN8855 support | expand |
On Mon, 9 Dec 2024 14:44:22 +0100 Christian Marangi wrote: > + regmap = devm_regmap_init(priv->dev, NULL, priv, > + &an8855_regmap_config); > + if (IS_ERR(regmap)) ^^^^^^^^^^^^^^ > + dev_err_probe(priv->dev, PTR_ERR(priv->dev), ^^^^^^^^^^^^^^^^^^ > + "regmap initialization failed\n"); wrong ptr?
On Mon, Dec 09, 2024 at 03:18:13PM -0800, Jakub Kicinski wrote: > On Mon, 9 Dec 2024 14:44:22 +0100 Christian Marangi wrote: > > + regmap = devm_regmap_init(priv->dev, NULL, priv, > > + &an8855_regmap_config); > > + if (IS_ERR(regmap)) > ^^^^^^^^^^^^^^ > > + dev_err_probe(priv->dev, PTR_ERR(priv->dev), > ^^^^^^^^^^^^^^^^^^ > > + "regmap initialization failed\n"); > > wrong ptr? yes wth... I'm sorry for all these stupid mistake for this series... Also hope we won't have to request multiple stable tag for this multi subsystem patch. Any hint on that?
On Tue, 10 Dec 2024 00:22:59 +0100 Christian Marangi wrote: > Also hope we won't have to request multiple stable tag for this multi > subsystem patch. Any hint on that? Sorry I haven't payed much attention to earlier discussions. Why multiple stable tags? AFAICT all trees will need patches 4 and 5, so we can put that on a stable tag / branch, the rest can go directly into respective trees (assuming the table tag has been merged in). No?
On Mon, Dec 09, 2024 at 03:40:30PM -0800, Jakub Kicinski wrote: > On Tue, 10 Dec 2024 00:22:59 +0100 Christian Marangi wrote: > > Also hope we won't have to request multiple stable tag for this multi > > subsystem patch. Any hint on that? > > Sorry I haven't payed much attention to earlier discussions. > Why multiple stable tags? AFAICT all trees will need patches > 4 and 5, so we can put that on a stable tag / branch, the rest > can go directly into respective trees (assuming the table tag > has been merged in). No? Yes in theory only MFD is really needed (as it does export the page symbol) - NVMEM can go in his own tree. (no need for stable tag) - mdio (require stable tag to correctly compile) - dsa/phy (no need for stable tag) So you are right, only one tag needed.
On Mon, Dec 09, 2024 at 03:18:13PM -0800, Jakub Kicinski wrote: > On Mon, 9 Dec 2024 14:44:22 +0100 Christian Marangi wrote: > > + regmap = devm_regmap_init(priv->dev, NULL, priv, > > + &an8855_regmap_config); > > + if (IS_ERR(regmap)) > ^^^^^^^^^^^^^^ > > + dev_err_probe(priv->dev, PTR_ERR(priv->dev), > ^^^^^^^^^^^^^^^^^^ > > + "regmap initialization failed\n"); > > wrong ptr? > -- > pw-bot: cr Also, why continue execution if devm_regmap_init() failed?
On Mon, Dec 09, 2024 at 02:44:22PM +0100, Christian Marangi wrote: > +int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, > + u8 page) __must_hold(&priv->bus->mdio_lock) > +{ > + struct mii_bus *bus = priv->bus; > + int ret; > + > + ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page); > + if (ret < 0) > + dev_err_ratelimited(&bus->dev, > + "failed to set an8855 mii page\n"); > + > + /* Cache current page if next mii read/write is for switch */ > + priv->current_page = page; > + return ret < 0 ? ret : 0; > +} > +EXPORT_SYMBOL_GPL(an8855_mii_set_page); You could keep the implementation more contained, and you could avoid exporting an8855_mii_set_page() and an8855_mfd_priv to the MDIO passthrough driver, if you implement a virtual regmap and give it to the MDIO passthrough child MFD device. If this bus supports only clause 22 accesses (and it looks like it does), you could expose a 16-bit regmap with a linear address space of 32 MDIO addresses x 65536 registers. The bus->read() of the MDIO bus passthrough just performs regmap_read(), and bus->write() just performs regmap_write(). The MFD driver decodes the regmap address into a PHY address and a regnum, and performs the page switching locally, if needed.
On Tue, Dec 10, 2024 at 11:15:29PM +0200, Vladimir Oltean wrote: > On Mon, Dec 09, 2024 at 02:44:22PM +0100, Christian Marangi wrote: > > +int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, > > + u8 page) __must_hold(&priv->bus->mdio_lock) > > +{ > > + struct mii_bus *bus = priv->bus; > > + int ret; > > + > > + ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page); > > + if (ret < 0) > > + dev_err_ratelimited(&bus->dev, > > + "failed to set an8855 mii page\n"); > > + > > + /* Cache current page if next mii read/write is for switch */ > > + priv->current_page = page; > > + return ret < 0 ? ret : 0; > > +} > > +EXPORT_SYMBOL_GPL(an8855_mii_set_page); > > You could keep the implementation more contained, and you could avoid > exporting an8855_mii_set_page() and an8855_mfd_priv to the MDIO > passthrough driver, if you implement a virtual regmap and give it to the > MDIO passthrough child MFD device. > > If this bus supports only clause 22 accesses (and it looks like it does), > you could expose a 16-bit regmap with a linear address space of 32 MDIO > addresses x 65536 registers. The bus->read() of the MDIO bus passthrough > just performs regmap_read(), and bus->write() just performs regmap_write(). > The MFD driver decodes the regmap address into a PHY address and a regnum, > and performs the page switching locally, if needed. Doesn't regmap add lots of overhead tho? Maybe I should really change the switch regmap to apply a save/restore logic? With an implementation like that current_page is not needed anymore. And I feel additional read/write are ok for switch OP. On mdio I can use the parent-mdio-bus property to get the bus directly without using MFD priv. What do you think?
> Doesn't regmap add lots of overhead tho?
Compared to what. MDIO operates over a 2.5MHz bus, assuming it is true
MDIO. The CPU overhead of regmap is probably negligible compared to
waiting for MDIO transactions to finish.
Andrew
On Tue, Dec 10, 2024 at 11:32:17PM +0100, Christian Marangi wrote: > Doesn't regmap add lots of overhead tho? Maybe I should really change > the switch regmap to apply a save/restore logic? > > With an implementation like that current_page is not needed anymore. > And I feel additional read/write are ok for switch OP. > > On mdio I can use the parent-mdio-bus property to get the bus directly > without using MFD priv. > > What do you think? If performance is a relevant factor at all, it will be hard to measure it, other than with synthetic tests (various mixes of switch and PHY register access). Though since you mention it, it would be interesting to see a comparison of the 3 arbitration methods. This could probably be all done from the an8855_mfd_probe() calling context: read a switch register and a PHY register 100K times and see how long it took, then read 2 switch registers and a PHY register 100K times, then 3 switch registers.... At some point, we should start seeing the penalty of the page restoration in Andrew's proposal, because that will be done after each switch register read. Just curious to put it into perspective and see how soon it starts to make a difference. And this test will also answer the regmap overhead issue.
On Wed, Dec 11, 2024 at 01:48:03AM +0200, Vladimir Oltean wrote: > On Tue, Dec 10, 2024 at 11:32:17PM +0100, Christian Marangi wrote: > > Doesn't regmap add lots of overhead tho? Maybe I should really change > > the switch regmap to apply a save/restore logic? > > > > With an implementation like that current_page is not needed anymore. > > And I feel additional read/write are ok for switch OP. > > > > On mdio I can use the parent-mdio-bus property to get the bus directly > > without using MFD priv. > > > > What do you think? > > If performance is a relevant factor at all, it will be hard to measure it, other > than with synthetic tests (various mixes of switch and PHY register access). > Though since you mention it, it would be interesting to see a comparison of the > 3 arbitration methods. This could probably be all done from the an8855_mfd_probe() > calling context: read a switch register and a PHY register 100K times and see how > long it took, then read 2 switch registers and a PHY register 100K times, then > 3 switch registers.... At some point, we should start seeing the penalty of the > page restoration in Andrew's proposal, because that will be done after each switch > register read. Just curious to put it into perspective and see how soon it starts > to make a difference. And this test will also answer the regmap overhead issue. Ok sorry for the delay as I had to tackle an annoying crypto driver... I was also curious about this and I hope I tested this correctly... The testing code is this. Following Vladimir testing and simple time comparision before and after. I used 100 times as 100k was very big. From the results we can derive our conclusions. static void test(struct an8855_mfd_priv *priv, struct regmap *regmap, struct regmap *regmap_phy) { ktime_t start_time, end_time; // struct mii_bus *bus = priv->bus; s64 elapsed_ns; u32 val; int times = 1; int i, j; start_time = ktime_get(); for (i = 0; i < 100; i++) { for (j = 0; j < times; j++) { regmap_read(regmap, 0x10005000, &val); } // mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); // // an8855_mii_set_page(priv, priv->switch_addr, 0); // __mdiobus_read(bus, priv->switch_addr, 0x1); // mutex_unlock(&bus->mdio_lock); regmap_read(regmap_phy, FIELD_PREP(GENMASK(20, 16), priv->switch_addr) | FIELD_PREP(GENMASK(15, 0), 0x1), &val); times++; } end_time = ktime_get(); elapsed_ns = ktime_to_ns(ktime_sub(end_time, start_time)); pr_info("Time spent in the code block: %lld ns\n", elapsed_ns); } With the code changed accordingly. switch regmap + page (proposed implementation) Time spent in the code block: 866179846 ns switch regmap + phy regmap (proposed implementation + PHY regmap) Time spent in the code block: 861326846 ns switch regmap restore (switch regmap read/set/restore page) Time spent in the code block: 1151011308 ns switch regmap restore + phy regmap (switch regmap read/set/restore pgae + PHY regmap) Time spent in the code block: 1147400462 ns We can see that: - as suggested regmap doesn't cause any performance penality. It does even produce better result. - the read/set/restore implementation gives worse performance. So I guess I will follow the path of regmap + cache page. What do you think?
On Sat, Dec 14, 2024 at 04:11:54PM +0100, Christian Marangi wrote: > We can see that: > - as suggested regmap doesn't cause any performance penality. It does > even produce better result. > - the read/set/restore implementation gives worse performance. > > So I guess I will follow the path of regmap + cache page. What do you > think? I'm not seeing results with the "times" variable changed, but in general, I guess the "switch regmap + page" and "switch regmap + phy regmap" will remain neck and neck in terms of performance, surpassing the "switch regmap restore" techniques more and more as "times" increases. So going with a PHY regmap probably sounds good.
On Tue, Dec 17, 2024 at 05:13:39PM +0200, Vladimir Oltean wrote: > On Sat, Dec 14, 2024 at 04:11:54PM +0100, Christian Marangi wrote: > > We can see that: > > - as suggested regmap doesn't cause any performance penality. It does > > even produce better result. > > - the read/set/restore implementation gives worse performance. > > > > So I guess I will follow the path of regmap + cache page. What do you > > think? > > I'm not seeing results with the "times" variable changed, but in > general, I guess the "switch regmap + page" and "switch regmap + phy > regmap" will remain neck and neck in terms of performance, surpassing > the "switch regmap restore" techniques more and more as "times" > increases. So going with a PHY regmap probably sounds good. Could you find a way to reuse Maxime's mdio-regmap.c driver? Either create separate regmaps for each PHY address, or make that driver accept a configuration which isn't limited to a single ctx->valid_addr?
diff --git a/MAINTAINERS b/MAINTAINERS index f3e3f6938824..7f4d7c48b6e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -721,6 +721,7 @@ F: Documentation/devicetree/bindings/mfd/airoha,an8855-mfd.yaml F: Documentation/devicetree/bindings/net/airoha,an8855-mdio.yaml F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml +F: drivers/mfd/airoha-an8855.c AIROHA ETHERNET DRIVER M: Lorenzo Bianconi <lorenzo@kernel.org> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ae23b317a64e..3a0b84991408 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -53,6 +53,16 @@ config MFD_ALTERA_SYSMGR using regmap_mmio accesses for ARM32 parts and SMC calls to EL3 for ARM64 parts. +config MFD_AIROHA_AN8855 + tristate "Airoha AN8855 Switch MFD" + select MFD_CORE + select MDIO_DEVICE + depends on NETDEVICES && OF + help + Support for the Airoha AN8855 Switch MFD. This is a SoC Switch + that provides various peripherals. Currently it provides a + DSA switch and a NVMEM provider. + config MFD_ACT8945A tristate "Active-semi ACT8945A" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e057d6d6faef..bcbeb36ab19d 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o +obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o obj-$(CONFIG_MFD_ACT8945A) += act8945a.o obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c new file mode 100644 index 000000000000..eeaea348aa41 --- /dev/null +++ b/drivers/mfd/airoha-an8855.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MFD driver for Airoha AN8855 Switch + */ + +#include <linux/mfd/airoha-an8855-mfd.h> +#include <linux/mfd/core.h> +#include <linux/mdio.h> +#include <linux/module.h> +#include <linux/phy.h> +#include <linux/regmap.h> + +static const struct mfd_cell an8855_mfd_devs[] = { + { + .name = "an8855-efuse", + .of_compatible = "airoha,an8855-efuse", + }, { + .name = "an8855-switch", + .of_compatible = "airoha,an8855-switch", + }, { + .name = "an8855-mdio", + .of_compatible = "airoha,an8855-mdio", + } +}; + +int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, + u8 page) __must_hold(&priv->bus->mdio_lock) +{ + struct mii_bus *bus = priv->bus; + int ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page); + if (ret < 0) + dev_err_ratelimited(&bus->dev, + "failed to set an8855 mii page\n"); + + /* Cache current page if next mii read/write is for switch */ + priv->current_page = page; + return ret < 0 ? ret : 0; +} +EXPORT_SYMBOL_GPL(an8855_mii_set_page); + +static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 *val) __must_hold(&bus->mdio_lock) +{ + int lo, hi, ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret < 0) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH, + upper_16_bits(reg)); + if (ret < 0) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW, + lower_16_bits(reg)); + if (ret < 0) + goto err; + + hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH); + if (hi < 0) { + ret = hi; + goto err; + } + lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW); + if (lo < 0) { + ret = lo; + goto err; + } + + *val = ((u16)hi << 16) | ((u16)lo & 0xffff); + + return 0; +err: + dev_err_ratelimited(&bus->dev, + "failed to read an8855 register\n"); + return ret; +} + +static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val) +{ + struct an8855_mfd_priv *priv = ctx; + struct mii_bus *bus = priv->bus; + u16 addr = priv->switch_addr; + int ret; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_read32(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 val) __must_hold(&bus->mdio_lock) +{ + int ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret < 0) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH, + upper_16_bits(reg)); + if (ret < 0) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW, + lower_16_bits(reg)); + if (ret < 0) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH, + upper_16_bits(val)); + if (ret < 0) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW, + lower_16_bits(val)); + if (ret < 0) + goto err; + + return 0; +err: + dev_err_ratelimited(&bus->dev, + "failed to write an8855 register\n"); + return ret; +} + +static int +an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val) +{ + struct an8855_mfd_priv *priv = ctx; + struct mii_bus *bus = priv->bus; + u16 addr = priv->switch_addr; + int ret; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_write32(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, + uint32_t write_val) +{ + struct an8855_mfd_priv *priv = ctx; + struct mii_bus *bus = priv->bus; + u16 addr = priv->switch_addr; + u32 val; + int ret; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_read32(bus, addr, reg, &val); + if (ret < 0) + goto exit; + + val &= ~mask; + val |= write_val; + ret = an8855_mii_write32(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static const struct regmap_range an8855_readable_ranges[] = { + regmap_reg_range(0x10000000, 0x10000fff), /* SCU */ + regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */ + regmap_reg_range(0x10002000, 0x10002fff), /* MCU */ + regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */ + regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */ + regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */ + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ + regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */ + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ + regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */ + regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */ + regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */ + regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */ + regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */ + regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */ + regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */ + regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */ + regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */ + regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */ + regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */ + regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */ + regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */ + regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */ + regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */ + regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */ + regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */ + regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */ +}; + +static const struct regmap_access_table an8855_readable_table = { + .yes_ranges = an8855_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges), +}; + +static const struct regmap_config an8855_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0xbfffffff, + .reg_read = an8855_regmap_read, + .reg_write = an8855_regmap_write, + .reg_update_bits = an8855_regmap_update_bits, + .disable_locking = true, + .rd_table = &an8855_readable_table, +}; + +static int an8855_mfd_probe(struct mdio_device *mdiodev) +{ + struct an8855_mfd_priv *priv; + struct regmap *regmap; + + priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->bus = mdiodev->bus; + priv->dev = &mdiodev->dev; + priv->switch_addr = mdiodev->addr; + /* no DMA for mdiobus, mute warning for DMA mask not set */ + priv->dev->dma_mask = &priv->dev->coherent_dma_mask; + + regmap = devm_regmap_init(priv->dev, NULL, priv, + &an8855_regmap_config); + if (IS_ERR(regmap)) + dev_err_probe(priv->dev, PTR_ERR(priv->dev), + "regmap initialization failed\n"); + + dev_set_drvdata(&mdiodev->dev, priv); + + return devm_mfd_add_devices(priv->dev, PLATFORM_DEVID_AUTO, an8855_mfd_devs, + ARRAY_SIZE(an8855_mfd_devs), NULL, 0, + NULL); +} + +static const struct of_device_id an8855_mfd_of_match[] = { + { .compatible = "airoha,an8855-mfd" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_mfd_of_match); + +static struct mdio_driver an8855_mfd_driver = { + .probe = an8855_mfd_probe, + .mdiodrv.driver = { + .name = "an8855", + .of_match_table = an8855_mfd_of_match, + }, +}; +mdio_module_driver(an8855_mfd_driver); + +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>"); +MODULE_DESCRIPTION("Driver for Airoha AN8855 MFD"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/airoha-an8855-mfd.h b/include/linux/mfd/airoha-an8855-mfd.h new file mode 100644 index 000000000000..56061566a079 --- /dev/null +++ b/include/linux/mfd/airoha-an8855-mfd.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MFD driver for Airoha AN8855 Switch + */ +#ifndef _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H +#define _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H + +#include <linux/bitfield.h> + +/* MII Registers */ +#define AN8855_PHY_SELECT_PAGE 0x1f +#define AN8855_PHY_PAGE GENMASK(2, 0) +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) +#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4) + +/* MII Registers Page 4 */ +#define AN8855_PBUS_MODE 0x10 +#define AN8855_PBUS_MODE_ADDR_FIXED 0x0 +#define AN8855_PBUS_MODE_ADDR_INCR BIT(15) +#define AN8855_PBUS_WR_ADDR_HIGH 0x11 +#define AN8855_PBUS_WR_ADDR_LOW 0x12 +#define AN8855_PBUS_WR_DATA_HIGH 0x13 +#define AN8855_PBUS_WR_DATA_LOW 0x14 +#define AN8855_PBUS_RD_ADDR_HIGH 0x15 +#define AN8855_PBUS_RD_ADDR_LOW 0x16 +#define AN8855_PBUS_RD_DATA_HIGH 0x17 +#define AN8855_PBUS_RD_DATA_LOW 0x18 + +struct an8855_mfd_priv { + struct device *dev; + struct mii_bus *bus; + + unsigned int switch_addr; + u16 current_page; +}; + +int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id, + u8 page); + +#endif
Add support for Airoha AN8855 Switch MFD that provide support for a DSA switch and a NVMEM provider. Also provide support for a virtual MDIO passthrough as the PHYs address for the switch are shared with the switch address Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- MAINTAINERS | 1 + drivers/mfd/Kconfig | 10 + drivers/mfd/Makefile | 1 + drivers/mfd/airoha-an8855.c | 278 ++++++++++++++++++++++++++ include/linux/mfd/airoha-an8855-mfd.h | 41 ++++ 5 files changed, 331 insertions(+) create mode 100644 drivers/mfd/airoha-an8855.c create mode 100644 include/linux/mfd/airoha-an8855-mfd.h