From patchwork Thu Dec 19 17:08:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13915411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA3A7E77184 for ; Thu, 19 Dec 2024 17:23:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IqoUewImG+TdN/K76GDrUghHXx1ox1BaE+aqhvOf1wk=; b=ocGIhPiOn2n7NzaILMp65WT49M BndN4xPyAGPsdU7goulkHfqQhbKb5LSF8RAbv8zdfqNdCRAec38VfE9VTYj/5wEE3R0t8nE7/U75q 6waCPn47xC9VzJk90M3iQn0cTv6lF9bX8u3dm7o0bYAj5ydYqs6Yu81urtHPfDujiqIr3vBh7LM73 Ra00WnZTQvNBkzgfYpdcZlFK9AhhyGlfM7CX7A+/nXpXohkbKht0J3igENSMLJ0qb637ZGvHlGP/7 gHHNvKBbroW3+tNrqOTzUPwaMP9dLZpKgyt9+f0vKVW3M0dbbhksZK1qJZQaWySuSMw3mESO9VXfP x8SOLNfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tOKFN-00000002XyW-44zI; Thu, 19 Dec 2024 17:23:37 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tOKFL-00000002XxL-3vre; Thu, 19 Dec 2024 17:23:36 +0000 X-UUID: d08a71a8be2b11ef9048ed6ed365623b-20241219 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IqoUewImG+TdN/K76GDrUghHXx1ox1BaE+aqhvOf1wk=; b=h/lDEVB29sTwq0zM1uq7ENuC76m+OmaW0lks2YKpMlJ5VNSq61PyEFPQYbx6U1nnAiobnGpT1aVY2eGOBX1g3NXI5Nqc7pZ+0NbdrSTVhdkL/GkD44IC11yTZSGxaXzAItx+rLz5n/NTYCwWQSMhl6YOYSMHAv2icuHYN3vgViw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.45,REQID:effbc28e-bf18-469a-9672-7a81ec4d1bc0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:-32768,SF:-32768,FILE:0,BULK:-32768,RULE:Rele ase_Ham,ACTION:release,TS:0 X-CID-META: VersionHash:6493067,CLOUDID:3e8b3e3c-e809-4df3-83cd-88f012b9e9ba,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: d08a71a8be2b11ef9048ed6ed365623b-20241219 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 812406920; Thu, 19 Dec 2024 10:08:06 -0700 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 20 Dec 2024 01:08:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 20 Dec 2024 01:08:03 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Mauro Carvalho Chehab CC: David Airlie , Simona Vetter , , , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Moudy Ho , Xavier Chang , Subject: [PATCH v3 7/7] media: mediatek: mdp3: Add programming flow for unsupported subsys ID hardware Date: Fri, 20 Dec 2024 01:08:00 +0800 Message-ID: <20241219170800.2957-8-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241219170800.2957-1-jason-jh.lin@mediatek.com> References: <20241219170800.2957-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241219_092335_970507_831CD939 X-CRM114-Status: GOOD ( 13.42 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org To support hardware without subsys IDs on new SoCs, add a programming flow that checks whether the subsys ID is valid. If the subsys ID is invalid, the flow will call 2 alternative CMDQ APIs: cmdq_pkt_assign() and cmdq_pkt_write_s_mask_value() to achieve the same functionality. Signed-off-by: Jason-JH.Lin --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 18 ++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 79 ++++++++++++++----- 2 files changed, 77 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index e5ccf673e152..0ee3354963db 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -321,7 +321,14 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, /* Enable mux settings */ for (index = 0; index < ctrl->num_sets; index++) { set = &ctrl->sets[index]; - cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, set->value); + if (set->subsys_id != CMDQ_SUBSYS_INVALID) { + cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, set->value); + } else { + /* only MMIO access, no need to check mminfro_offset */ + cmdq_pkt_assign(&cmd->pkt, CMDQ_THR_SPR_IDX0, CMDQ_ADDR_HIGH(set->reg)); + cmdq_pkt_write_s_value(&cmd->pkt, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(set->reg), set->value); + } } /* Config sub-frame information */ for (index = (num_comp - 1); index >= 0; index--) { @@ -376,7 +383,14 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, /* Disable mux settings */ for (index = 0; index < ctrl->num_sets; index++) { set = &ctrl->sets[index]; - cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, 0); + if (set->subsys_id != CMDQ_SUBSYS_INVALID) { + cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, 0); + } else { + /* only MMIO access, no need to check mminfro_offset */ + cmdq_pkt_assign(&cmd->pkt, CMDQ_THR_SPR_IDX0, CMDQ_ADDR_HIGH(set->reg)); + cmdq_pkt_write_s_value(&cmd->pkt, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(set->reg), 0); + } } return 0; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 681906c16419..e20f9d080db9 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -9,17 +9,44 @@ #include "mtk-mdp3-cmdq.h" -#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask) \ -do { \ - typeof(mask) (m) = (mask); \ - cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst), \ - (val), \ - (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ - (0xffffffff) : (m)); \ +#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask) \ +do { \ + typeof(cmd) (_c) = (cmd); \ + typeof(id) (_i) = (id); \ + typeof(base) (_b) = (base); \ + typeof(ofst) (_o) = (ofst); \ + typeof(val) (_v) = (val); \ + typeof(mask) (_m) = (mask); \ + _m = ((_m & (ofst##_MASK)) == (ofst##_MASK)) ? 0xffffffff : _m; \ + if (_i != CMDQ_SUBSYS_INVALID) { \ + cmdq_pkt_write_mask(&_c->pkt, _i, _b + _o, _v, _m); \ + } else { \ + /* only MMIO access, no need to check mminfro_offset */ \ + cmdq_pkt_assign(&_c->pkt, CMDQ_THR_SPR_IDX0, \ + CMDQ_ADDR_HIGH(_b)); \ + cmdq_pkt_write_s_mask_value(&_c->pkt, CMDQ_THR_SPR_IDX0,\ + CMDQ_ADDR_LOW(_b + _o), \ + _v, _m); \ + } \ } while (0) -#define MM_REG_WRITE(cmd, id, base, ofst, val) \ - cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val)) +#define MM_REG_WRITE(cmd, id, base, ofst, val) \ +do { \ + typeof(cmd) (_c) = (cmd); \ + typeof(id) (_i) = (id); \ + typeof(base) (_b) = (base); \ + typeof(ofst) (_o) = (ofst); \ + typeof(val) (_v) = (val); \ + if (_i != CMDQ_SUBSYS_INVALID) { \ + cmdq_pkt_write(&_c->pkt, _i, _b + _o, _v); \ + } else { \ + /* only MMIO access, no need to check mminfro_offset */ \ + cmdq_pkt_assign(&_c->pkt, CMDQ_THR_SPR_IDX0, \ + CMDQ_ADDR_HIGH(_b)); \ + cmdq_pkt_write_s_value(&_c->pkt, CMDQ_THR_SPR_IDX0, \ + CMDQ_ADDR_LOW(_b + _o), _v); \ + } \ +} while (0) #define MM_REG_WAIT(cmd, evt) \ do { \ @@ -49,17 +76,33 @@ do { \ cmdq_pkt_set_event(&((c)->pkt), (e)); \ } while (0) -#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask) \ -do { \ - typeof(_mask) (_m) = (_mask); \ - cmdq_pkt_poll_mask(&((cmd)->pkt), id, \ - (base) + (ofst), (val), \ - (((_m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ - (0xffffffff) : (_m)); \ +#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, mask) \ +do { \ + typeof(cmd) (_c) = (cmd); \ + typeof(id) (_i) = (id); \ + typeof(base) (_b) = (base); \ + typeof(ofst) (_o) = (ofst); \ + typeof(val) (_v) = (val); \ + typeof(mask) (_m) = (mask); \ + _m = ((_m & (ofst##_MASK)) == (ofst##_MASK)) ? 0xffffffff : _m; \ + if (_i != CMDQ_SUBSYS_INVALID) \ + cmdq_pkt_poll_mask(&_c->pkt, _i, _b + _o, _v, _m); \ + else /* POLL not support SPR, so use cmdq_pkt_poll_addr() */ \ + cmdq_pkt_poll_addr(&_c->pkt, _b + _o, _v, _m); \ } while (0) -#define MM_REG_POLL(cmd, id, base, ofst, val) \ - cmdq_pkt_poll(&((cmd)->pkt), id, (base) + (ofst), (val)) +#define MM_REG_POLL(cmd, id, base, ofst, val) \ +do { \ + typeof(cmd) (_c) = (cmd); \ + typeof(id) (_i) = (id); \ + typeof(base) (_b) = (base); \ + typeof(ofst) (_o) = (ofst); \ + typeof(val) (_v) = (val); \ + if (_i != CMDQ_SUBSYS_INVALID) \ + cmdq_pkt_poll(&_c->pkt, _i, _b + _o, _v); \ + else /* POLL not support SPR, so use cmdq_pkt_poll_addr() */ \ + cmdq_pkt_poll_addr(&_c->pkt, _b + _o, _v, 0xffffffff); \ +} while (0) enum mtk_mdp_comp_id { MDP_COMP_NONE = -1, /* Invalid engine */