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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-38bf3215023sm11095390f8f.9.2025.01.20.10.48.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jan 2025 10:48:15 -0800 (PST) From: Christian Marangi To: Chaotian Jing , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Wenbin Mei , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, upstream@airoha.com Cc: Christian Marangi Subject: [PATCH v2 2/2] mmc: mtk-sd: add support for AN7581 MMC Host Date: Mon, 20 Jan 2025 19:47:02 +0100 Message-ID: <20250120184728.18325-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250120184728.18325-1-ansuelsmth@gmail.com> References: <20250120184728.18325-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250120_104818_078780_7BA6D181 X-CRM114-Status: GOOD ( 19.13 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add support for AN7581 MMC Host. The MMC Host controller is based on mt7622 with the difference of not having regulator supply and state_uhs pins and hclk clock. Some minor fixes are applied to check if the state_uhs pins are defined and make hclk optional for the new airoha compatible. Signed-off-by: Christian Marangi --- Changes v2: - Drop redundant if condition where regulator is not supported - Correctly set pin in msdc_ops_switch_volt drivers/mmc/host/mtk-sd.c | 59 +++++++++++++++++++++++++++++---------- 1 file changed, 45 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index efb0d2d5716b..f76f20502409 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -666,6 +666,20 @@ static const struct mtk_mmc_compatible mt8196_compat = { .support_new_rx = true, }; +static const struct mtk_mmc_compatible an7581_compat = { + .clk_div_bits = 12, + .recheck_sdio_irq = true, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .stop_dly_sel = 3, + .enhance_rx = true, + .support_64g = false, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, @@ -680,7 +694,7 @@ static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, - + { .compatible = "airoha,an7581-mmc", .data = &an7581_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -1614,12 +1628,15 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) return ret; } - /* Apply different pinctrl settings for different signal voltage */ - if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) - pinctrl_select_state(host->pinctrl, host->pins_uhs); - else - pinctrl_select_state(host->pinctrl, host->pins_default); } + + /* Apply different pinctrl settings for different signal voltage */ + if (!IS_ERR(mmc->supply.vqmmc) && + ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + pinctrl_select_state(host->pinctrl, host->pins_uhs); + else + pinctrl_select_state(host->pinctrl, host->pins_default); + return 0; } @@ -1699,7 +1716,9 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); } - pinctrl_select_state(host->pinctrl, host->pins_uhs); + /* Skip setting uhs pins if not supported */ + if (host->pins_uhs) + pinctrl_select_state(host->pinctrl, host->pins_uhs); } else { dev_pm_clear_wake_irq(host->dev); } @@ -2816,9 +2835,12 @@ static int msdc_of_clock_parse(struct platform_device *pdev, if (IS_ERR(host->src_clk)) return PTR_ERR(host->src_clk); - host->h_clk = devm_clk_get(&pdev->dev, "hclk"); - if (IS_ERR(host->h_clk)) - return PTR_ERR(host->h_clk); + /* AN7581 SoC doesn't have hclk */ + if (!device_is_compatible(&pdev->dev, "airoha,an7581-mmc")) { + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(host->h_clk)) + return PTR_ERR(host->h_clk); + } host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); if (IS_ERR(host->bus_clk)) @@ -2926,10 +2948,13 @@ static int msdc_drv_probe(struct platform_device *pdev) return PTR_ERR(host->pins_default); } - host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); - if (IS_ERR(host->pins_uhs)) { - dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); - return PTR_ERR(host->pins_uhs); + /* AN7581 doesn't have state_uhs pins */ + if (!device_is_compatible(&pdev->dev, "airoha,an7581-mmc")) { + host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); + if (IS_ERR(host->pins_uhs)) { + dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); + return PTR_ERR(host->pins_uhs); + } } /* Support for SDIO eint irq ? */ @@ -3010,6 +3035,12 @@ static int msdc_drv_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Cannot ungate clocks!\n"); goto release_clk; } + + /* AN7581 without regulator require tune to OCR values */ + if (device_is_compatible(&pdev->dev, "airoha,an7581-mmc") && + !mmc->ocr_avail) + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + msdc_init_hw(host); if (mmc->caps2 & MMC_CAP2_CQE) {