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[v2,1/2] dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle property

Message ID 20250202-en7581-pcie-pbus-csr-v2-1-65dcb201c9a9@kernel.org (mailing list archive)
State New
Headers show
Series PCI: mediatek-gen3: Set PBUS_CSR regs for Airoha EN7581 SoC. | expand

Commit Message

Lorenzo Bianconi Feb. 2, 2025, 7:34 p.m. UTC 
Introduce the mediatek,pbus-csr property for the pbus-csr syscon node
available on EN7581 SoC. The airoha pbus-csr block provides a configuration
interface for the PBUS controller used to detect if a given address is on
PCIE0, PCIE1 or PCIE2.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml          | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index f05aab2b1addcac91d4685d7d94f421814822b92..02f2cd9bcf007c1f16b18b1330a88ce43807a9be 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -109,6 +109,12 @@  properties:
   power-domains:
     maxItems: 1
 
+  mediatek,pbus-csr:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon node used to detect if a given address is on
+      the PCIe ports.
+
   '#interrupt-cells':
     const: 1
 
@@ -168,6 +174,8 @@  allOf:
           minItems: 1
           maxItems: 2
 
+        mediatek,pbus-csr: false
+
   - if:
       properties:
         compatible:
@@ -197,6 +205,8 @@  allOf:
           minItems: 1
           maxItems: 2
 
+        mediatek,pbus-csr: false
+
   - if:
       properties:
         compatible:
@@ -224,6 +234,8 @@  allOf:
           minItems: 1
           maxItems: 2
 
+        mediatek,pbus-csr: false
+
   - if:
       properties:
         compatible: