diff mbox series

[3/5] soc: mediatek: Add components to support PQ in display path for MT8196

Message ID 20250211025317.399534-4-sunny.shen@mediatek.com (mailing list archive)
State New
Headers show
Series Add components to support PQ in display path for MT8196 | expand

Commit Message

Sunny Shen Feb. 11, 2025, 2:52 a.m. UTC 
Due to the path mux design of the MT8196, the following components
need to be configured into mutex and mmsys to support
Picture Quality (PQ) in the display path:CCORR0, CCORR1, DITHER0,
GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 drivers/soc/mediatek/mt8196-mmsys.h    | 70 +++++++++++++++++++++++++-
 drivers/soc/mediatek/mtk-mutex.c       | 17 +++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  5 ++
 3 files changed, 90 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/soc/mediatek/mt8196-mmsys.h b/drivers/soc/mediatek/mt8196-mmsys.h
index 03d1210d2b80..b686d5029219 100644
--- a/drivers/soc/mediatek/mt8196-mmsys.h
+++ b/drivers/soc/mediatek/mt8196-mmsys.h
@@ -68,6 +68,22 @@ 
 #define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY7		BIT(2)
 
 /* DISPSYS0 */
+#define MT8196_DISP_CCORR0_SEL				0xd28
+#define MT8196_DISP_CCORR0_FROM_TDSHP0				BIT(1)
+#define MT8196_DISP_CCORR0_SOUT				0xd2c
+#define MT8196_DISP_CCORR0_TO_CCORR1				BIT(0)
+#define MT8196_DISP_CCORR1_SEL				0xd30
+#define MT8196_DISP_CCORR1_FROM_CCORR0				BIT(0)
+#define MT8196_DISP_CCORR1_SOUT				0xd34
+#define MT8196_DISP_CCORR1_TO_GAMMA0				BIT(0)
+#define MT8196_DISP_GAMMA0_SEL				0xd58
+#define MT8196_DISP_GAMMA0_FROM_CCORR1				BIT(0)
+#define MT8196_DISP_POSTMASK0_SOUT			0xd68
+#define MT8196_DISP_POSTMASK0_TO_DITHER0			0x0
+#define MT8196_DISP_TDSHP0_SOUT				0xd70
+#define MT8196_DISP_TDSHP0_TO_CCORR0				BIT(1)
+#define MT8196_MDP_RSZ0_MOUT_EN				0xd78
+#define MT8196_MDP_RSZ0_TO_TDSHP0				BIT(0)
 #define MT8196_PANEL_COMP_OUT_CB1_MOUT_EN		0xd84
 #define MT8196_DISP_TO_DLO_RELAY1				BIT(1)
 #define MT8196_PANEL_COMP_OUT_CB2_MOUT_EN		0xd88
@@ -75,12 +91,14 @@ 
 #define MT8196_PANEL_COMP_OUT_CB3_MOUT_EN		0xd8c
 #define MT8196_DISP_TO_DLO_RELAY3				BIT(3)
 #define MT8196_PQ_IN_CB0_MOUT_EN			0xdd0
+#define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0				BIT(0)
 #define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6				BIT(2)
-
 #define MT8196_PQ_IN_CB1_MOUT_EN			0xdd4
 #define MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7				BIT(3)
 #define MT8196_PQ_IN_CB8_MOUT_EN			0xdf0
 #define MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8				BIT(4)
+#define MT8196_PQ_OUT_CB0_MOUT_EN			0xe3c
+#define MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1		BIT(1)
 #define MT8196_PQ_OUT_CB6_MOUT_EN			0xe54
 #define MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1		BIT(1)
 #define MT8196_PQ_OUT_CB7_MOUT_EN			0xe58
@@ -314,11 +332,13 @@  static const struct mtk_mmsys_routes mmsys_mt8196_ovl1_routing_table[] = {
 };
 
 /*
- * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ_OUT_CB6 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1
+ * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ (MDP_RSZ0/TDSHP0/CCORR0/CCORR1/GAMMA0/POSTMASK0/DITHER0)
+ *       -> PQ_OUT_CB0 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1
  * ext:  DLI_ASYNC1-> PQ_IN_CB1 -> PQ_OUT_CB7 -> PANEL_COMP_OUT_CB2 -> DLO_ASYNC2
  */
 static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = {
 	{
+	/* main: PQ bypass */
 		DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_DLO_ASYNC1,
 		MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6,
 		MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6
@@ -331,6 +351,52 @@  static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = {
 		MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1,
 		MT8196_DISP_TO_DLO_RELAY1
 	}, {
+	/* main: PQ path */
+		DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_MDP_RSZ0,
+		MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0,
+		MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0
+	}, {
+		DDP_COMPONENT_MDP_RSZ0, DDP_COMPONENT_TDSHP0,
+		MT8196_MDP_RSZ0_MOUT_EN, MT8196_MDP_RSZ0_TO_TDSHP0,
+		MT8196_MDP_RSZ0_TO_TDSHP0
+	}, {
+		DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0,
+		MT8196_DISP_TDSHP0_SOUT, MT8196_DISP_TDSHP0_TO_CCORR0,
+		MT8196_DISP_TDSHP0_TO_CCORR0
+	}, {
+		DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0,
+		MT8196_DISP_CCORR0_SEL, MT8196_DISP_CCORR0_FROM_TDSHP0,
+		MT8196_DISP_CCORR0_FROM_TDSHP0
+	}, {
+		DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1,
+		MT8196_DISP_CCORR0_SOUT, MT8196_DISP_CCORR0_TO_CCORR1,
+		MT8196_DISP_CCORR0_TO_CCORR1
+	}, {
+		DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1,
+		MT8196_DISP_CCORR1_SEL, MT8196_DISP_CCORR1_FROM_CCORR0,
+		MT8196_DISP_CCORR1_FROM_CCORR0
+	}, {
+		DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0,
+		MT8196_DISP_CCORR1_SOUT, MT8196_DISP_CCORR1_TO_GAMMA0,
+		MT8196_DISP_CCORR1_TO_GAMMA0
+	}, {
+		DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0,
+		MT8196_DISP_GAMMA0_SEL, MT8196_DISP_GAMMA0_FROM_CCORR1,
+		MT8196_DISP_GAMMA0_FROM_CCORR1
+	}, {
+		DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_DITHER0,
+		MT8196_DISP_POSTMASK0_SOUT, MT8196_DISP_POSTMASK0_TO_DITHER0,
+		MT8196_DISP_POSTMASK0_TO_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1,
+		MT8196_PQ_OUT_CB0_MOUT_EN, MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1,
+		MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1
+	}, {
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1,
+		MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1,
+		MT8196_DISP_TO_DLO_RELAY1
+	}, {
+	/* ext */
 		DDP_COMPONENT_DLI_ASYNC1, DDP_COMPONENT_DLO_ASYNC2,
 		MT8196_PQ_IN_CB1_MOUT_EN, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7,
 		MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 51db6f2a05ae..9c895566dfb2 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -262,6 +262,11 @@ 
 #define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6	(32 + 17)
 
 /* DISP0 */
+
+#define MT8196_MUTEX_MOD0_DISP_CCORR0		6
+#define MT8196_MUTEX_MOD0_DISP_CCORR1		7
+#define MT8196_MUTEX_MOD0_DISP_DITHER0		14
+
 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0	16
 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1	17
 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8	24
@@ -269,6 +274,11 @@ 
 #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2	(32 + 2)
 #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3	(32 + 3)
 
+#define MT8196_MUTEX_MOD1_DISP_GAMMA0		(32 + 9)
+#define MT8196_MUTEX_MOD1_DISP_POSTMASK0	(32 + 14)
+#define MT8196_MUTEX_MOD1_DISP_MDP_RSZ0		(32 + 18)
+#define MT8196_MUTEX_MOD1_DISP_TDSHP0		(32 + 21)
+
 /* DISP1 */
 #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21	1
 #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22	2
@@ -678,6 +688,13 @@  static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
 };
 
 static const u8 mt8196_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_CCORR0] = MT8196_MUTEX_MOD0_DISP_CCORR0,
+	[DDP_COMPONENT_CCORR1] = MT8196_MUTEX_MOD0_DISP_CCORR1,
+	[DDP_COMPONENT_DITHER0] = MT8196_MUTEX_MOD0_DISP_DITHER0,
+	[DDP_COMPONENT_GAMMA0] = MT8196_MUTEX_MOD1_DISP_GAMMA0,
+	[DDP_COMPONENT_MDP_RSZ0] = MT8196_MUTEX_MOD1_DISP_MDP_RSZ0,
+	[DDP_COMPONENT_POSTMASK0] = MT8196_MUTEX_MOD1_DISP_POSTMASK0,
+	[DDP_COMPONENT_TDSHP0] = MT8196_MUTEX_MOD1_DISP_TDSHP0,
 	[DDP_COMPONENT_OVL0_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2,
 	[DDP_COMPONENT_OVL0_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3,
 	[DDP_COMPONENT_OVL0_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4a0b10567581..250054ca5523 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -25,6 +25,8 @@  enum mtk_ddp_comp_id {
 	DDP_COMPONENT_AAL1,
 	DDP_COMPONENT_BLS,
 	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_CCORR0 = DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_CCORR1,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER0,
@@ -51,6 +53,7 @@  enum mtk_ddp_comp_id {
 	DDP_COMPONENT_DVO0,
 	DDP_COMPONENT_ETHDR_MIXER,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_GAMMA0 = DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_MDP_RDMA0,
 	DDP_COMPONENT_MDP_RDMA1,
 	DDP_COMPONENT_MDP_RDMA2,
@@ -59,6 +62,7 @@  enum mtk_ddp_comp_id {
 	DDP_COMPONENT_MDP_RDMA5,
 	DDP_COMPONENT_MDP_RDMA6,
 	DDP_COMPONENT_MDP_RDMA7,
+	DDP_COMPONENT_MDP_RSZ0,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_MERGE1,
 	DDP_COMPONENT_MERGE2,
@@ -130,6 +134,7 @@  enum mtk_ddp_comp_id {
 	DDP_COMPONENT_RDMA1,
 	DDP_COMPONENT_RDMA2,
 	DDP_COMPONENT_RDMA4,
+	DDP_COMPONENT_TDSHP0,
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,