| Message ID | 20250211113409.1517534-9-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for MT8195/88 DPI, HDMIv2 and DDCv2 | expand |
On Tue, 2025-02-11 at 12:33 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller > (afifo) supports outputting either one or two pixels per round > regardless of the input being 1T1P or 1T2P. > > Add a `output_1pixel` member to struct mtk_dpi_conf which, if > set, will enable outputting one pixel per clock. > > In case the input is two pixel per clock (1T2P), the AFIFO HW > will automatically (and internally) convert it to 1T1P. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 6493c7e2fae4..5c15c8935916 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -148,6 +148,8 @@ struct mtk_dpi_factor { > * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. > * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed > * for DPI registers access. > + * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per > + * round, the DPI hardware will internally transform it to 1T1P. > */ > struct mtk_dpi_conf { > const struct mtk_dpi_factor *dpi_factor; > @@ -170,6 +172,7 @@ struct mtk_dpi_conf { > u32 pixels_per_iter; > bool edge_cfg_in_mmsys; > bool clocked_by_hdmi; > + bool output_1pixel; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) > @@ -655,7 +658,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > if (dpi->conf->support_direct_pin) { > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > mtk_dpi_config_2n_h_fre(dpi); > - mtk_dpi_dual_edge(dpi); > + > + /* DPI can connect to either an external bridge or the internal HDMI encoder */ > + if (dpi->conf->output_1pixel) > + mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN); > + else > + mtk_dpi_dual_edge(dpi); > + > mtk_dpi_config_disable_edge(dpi); > } > if (dpi->conf->input_2p_en_bit && dpi->conf->input_2pixel) { > -- > 2.48.1 >
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 6493c7e2fae4..5c15c8935916 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -148,6 +148,8 @@ struct mtk_dpi_factor { * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed * for DPI registers access. + * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per + * round, the DPI hardware will internally transform it to 1T1P. */ struct mtk_dpi_conf { const struct mtk_dpi_factor *dpi_factor; @@ -170,6 +172,7 @@ struct mtk_dpi_conf { u32 pixels_per_iter; bool edge_cfg_in_mmsys; bool clocked_by_hdmi; + bool output_1pixel; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -655,7 +658,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, if (dpi->conf->support_direct_pin) { mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); + + /* DPI can connect to either an external bridge or the internal HDMI encoder */ + if (dpi->conf->output_1pixel) + mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN); + else + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); } if (dpi->conf->input_2p_en_bit && dpi->conf->input_2pixel) {
On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller (afifo) supports outputting either one or two pixels per round regardless of the input being 1T1P or 1T2P. Add a `output_1pixel` member to struct mtk_dpi_conf which, if set, will enable outputting one pixel per clock. In case the input is two pixel per clock (1T2P), the AFIFO HW will automatically (and internally) convert it to 1T1P. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)