From patchwork Wed Feb 12 10:00:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13971517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C489C021A1 for ; Wed, 12 Feb 2025 10:20:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IeX9ikM7qS7F8rSqXrVDULTo7O/yPT1ppENsEVgvV24=; b=VprXCr+vAZKLw9HR9VuJ+0Nhyb C6tU1mR0r+2YAhjou3tVQtB31NAWKBHRmIi1Cc49MQPe+aZMPRI2AJQwV7gLanXUQQ+/2I+F96GQ8 0waOJJ06M9/1IZBbil1fMSWgUtqgnHoltKesWnidqBgKJ3+BLp3D70RKsESto1awav5JNxyqKKW49 KO3ievk6jV5B3JkdeyAB8AjhpflhSOPgco6RxH5D5B2x+m5ihNeKTBVMvjIYqXwS3bJqcmc5ruQ6P YXVo+W3GRCqDoHkDwc8QJxPJae5QJn5XzXQQwpFv5hj7XVxvKNhqSn09D8P3ijFKFU9DZP4SXsXxt pImQe/7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1ti9ql-00000006xkH-3U9P; Wed, 12 Feb 2025 10:20:11 +0000 Received: from bali.collaboradmins.com ([2a01:4f8:201:9162::2]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1ti9Xb-00000006tgK-1cpz; Wed, 12 Feb 2025 10:00:24 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739354420; bh=d5JGq0sUdyIIpGFlmDy/NrRn+DMMIEoFQE/gdpvPLIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hh0YKGzrLkM03n/WuJ+WvxtxJ9D5LNSsEjkiB1EvozeoTz0neSip9ecPXqVS+lntC ur43Oi0PKu/rI8xjtbz4P19ICdo873hxSuPbQ5Tv205QR9BdwTBor7P1kQzVLsiqRV Q0HO+DXxjO7edoajnGd9ANe2FTKmKvkHKlBs/cNQgu7mlatV+gpr22HDAWdLDlKgAC vwCaFnqBLe3InFvhpPYtp7E7ueHQ9uXCQGxUP9uUGXolHiYr0BsvG20w4s+fdNGq6s g/92Xal6ZF6T0OkQRjTLVwdHr99pHwHKPjEXhndUt3YyYxdr9lb9QIKWFrudpCqtpE wrT9RMuq8KqWA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5FF0817E1551; Wed, 12 Feb 2025 11:00:20 +0100 (CET) From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: angelogioacchino.delregno@collabora.com, shawn.sung@mediatek.com, fparent@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, pablo.sun@mediatek.com, kernel@collabora.com Subject: [PATCH v1 4/8] soc: mediatek: mt8188-mmsys: Migrate to MMSYS_ROUTE() macro Date: Wed, 12 Feb 2025 11:00:08 +0100 Message-ID: <20250212100012.33001-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250212100012.33001-1-angelogioacchino.delregno@collabora.com> References: <20250212100012.33001-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_020023_646057_835BB7DB X-CRM114-Status: UNSURE ( 9.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Change the initialization data in the arrays of structure mtk_mmsys_routes to make use of the MMSYS_ROUTE() macro: this will make sure that each array entry's SEL value fits in its corresponding register mask with a compile time check. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8188-mmsys.h | 257 ++++++++++++---------------- 1 file changed, 108 insertions(+), 149 deletions(-) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index a1d63be0a73d..befd293e86c3 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -202,158 +202,117 @@ static const u8 mmsys_mt8188_vdo1_rst_tb[] = { }; static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, - MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, - MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, - MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, - MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, - MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, - MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, - MT8188_VDO0_DSC_WARP_SEL, - MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, - MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, - MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, - MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, - MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, - MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK, - MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DISP_DITHER0_SEL_OUT, - MT8188_SOUT_DISP_DITHER0_TO_MASK, - MT8188_SOUT_DISP_DITHER0_TO_DSI0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, - MT8188_VDO0_DISP_DITHER0_SEL_OUT, - MT8188_SOUT_DISP_DITHER0_TO_MASK, - MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, - MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, - MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE - }, + MMSYS_ROUTE(OVL0, RDMA0, + MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0), + MMSYS_ROUTE(OVL0, WDMA0, + MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, + MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0), + MMSYS_ROUTE(OVL0, RDMA0, + MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, + MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, + MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DITHER0, MERGE0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DITHER0, DSC0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, + MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0), + MMSYS_ROUTE(DITHER0, DP_INTF0, + MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0), + MMSYS_ROUTE(DSC0, MERGE0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, + MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(DSC0, DSI0, + MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, + MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(RDMA0, COLOR0, + MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0), + MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0), + MMSYS_ROUTE(DITHER0, DSI0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DSI0), + MMSYS_ROUTE(DITHER0, DP_INTF0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0), + MMSYS_ROUTE(MERGE0, DP_INTF0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DP_INTF0), + MMSYS_ROUTE(MERGE0, DPI0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), + MMSYS_ROUTE(MERGE0, WDMA0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0), + MMSYS_ROUTE(MERGE0, DSC0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN), + MMSYS_ROUTE(DSC0, DSI0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0), + MMSYS_ROUTE(DSC0, MERGE0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE), }; static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { - { - DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, - MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), - MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 - }, { - DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, - MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), - MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 - }, { - DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, - MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), - MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 - }, { - DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN1_SEL - }, { - DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN2_SEL - }, { - DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN3_SEL - }, { - DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), - MT8188_SOUT_TO_MIXER_IN4_SEL - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), - MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL - }, { - DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT - }, { - DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, - MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), - MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), - MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER - }, { - DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, - MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), - MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, - MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), - MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, - MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), - MT8188_MERGE4_SOUT_TO_DPI1_SEL - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, - MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), - MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, - MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), - MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL - } + MMSYS_ROUTE(MDP_RDMA0, MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0), + MMSYS_ROUTE(MDP_RDMA1, MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1), + MMSYS_ROUTE(MDP_RDMA2, MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2), + MMSYS_ROUTE(MERGE1, ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL), + MMSYS_ROUTE(MERGE2, ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL), + MMSYS_ROUTE(MERGE3, ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL), + MMSYS_ROUTE(MERGE4, ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL), + MMSYS_ROUTE(MERGE1, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT), + MMSYS_ROUTE(MERGE2, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT), + MMSYS_ROUTE(MERGE3, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT), + MMSYS_ROUTE(MERGE4, ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER), + MMSYS_ROUTE(ETHDR_MIXER, MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT), + MMSYS_ROUTE(MERGE5, DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT), + MMSYS_ROUTE(MERGE5, DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL), + MMSYS_ROUTE(MERGE5, DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT), + MMSYS_ROUTE(MERGE5, DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL), }; #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */