From patchwork Thu Feb 13 11:20:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13973144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7A46C021A4 for ; Thu, 13 Feb 2025 11:23:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=O0/VEQPkVeTKEskK9eKGdYYLELDxmZ17YrjDW20VZ+Y=; b=W3+AfqdATCci+GQHT3zSwkI4YM 1qR73BtjBN5K0vU+mguu/kh5NOSqT8v5FSzd/IFNTnrqNAdupbCuTHiyFNnNUdLHEPgqlTPFdx3BC QQmYNkr9OoYCVQQfxL9TvQ3hp/iRBI+acbfwdmBeXKpFAdDi0gcfXseHosYF0uJTw4UC3kbro8K0d XOMuQepIwVo0PXwd1nXIxwNix15l0Lh8AK9hi4iYbs66um8u9Cc4vKzXMI+KNKAtn1wgpW6rim2yn dniaEnPmpZp7O8F80U+IUdbDJo6AMTzxWKt9zpnIo9EVsueAv1TjjMaeVV/tdn7qPgeO2+jlrA5DR HLj4Jizg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tiXK0-0000000ApVj-3T9N; Thu, 13 Feb 2025 11:23:56 +0000 Received: from bali.collaboradmins.com ([148.251.105.195]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tiXH0-0000000Aod4-0FrX; Thu, 13 Feb 2025 11:20:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739445648; bh=E2XNV4WJzLYKlsC0jrTYob1TsNvbS4I9eUsDpDlD9hg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hrue+E5JAAlkh3h58w7Dv25y3vOaS+suQ4LGN1AfmBJR9YKITpfCS915G5Me44tb/ vy2MibWdjwLCnjwIsJVw68TZ5QzgwSuGe7zJelA4YMRZLFphlc01GgBPaJRom57kZd uhcKbb7u/WlcbshjBn7Jw0x79h1KP2tgz5zqT3Ws46OLSCpffksyc3dNYsCPex7eXa iggeV8hOSE9lgRBm32h3Eg9aDDWSSh8/rpEtRlFuQa1NjgcbfTARYja9WAmpLsniUu PcfJIltLs1UNQymaq7O4CZCUZ6Mz2fY9Y+POGaJF3QbuVGdvWogjntmVOEKhyiq946 X+Z+KnaBFrYAw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id D684617E0E93; Thu, 13 Feb 2025 12:20:47 +0100 (CET) From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, pablo.sun@mediatek.com Subject: [PATCH v1 1/3] arm64: dts: mediatek: mt8195: Add base display controller graph Date: Thu, 13 Feb 2025 12:20:06 +0100 Message-ID: <20250213112008.56394-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250213112008.56394-1-angelogioacchino.delregno@collabora.com> References: <20250213112008.56394-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250213_032050_247950_9093BF3C X-CRM114-Status: UNSURE ( 8.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The display related IPs in MT8195 are flexible and support being interconnected with different instances of DDP IPs and/or with different DDP IPs, forming a full Display Data Path that ends with an actual display output, which is board specific. Add a common graph in the main mt8195.dtsi devicetree, which is shared between all of the currently supported boards. All boards featuring any display functionality will extend this common graph to hook the display controller of the SoC to their specific output port(s). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index f013dbad9dc4..4f2dc0a75566 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3142,6 +3142,23 @@ ovl0: ovl@1c000000 { clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1c002000 { @@ -3152,6 +3169,25 @@ rdma0: rdma@1c002000 { clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -3161,6 +3197,25 @@ color0: color@1c003000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -3170,6 +3225,25 @@ ccorr0: ccorr@1c004000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -3179,6 +3253,25 @@ aal0: aal@1c005000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -3188,6 +3281,25 @@ gamma0: gamma@1c006000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@1c007000 { @@ -3197,6 +3309,23 @@ dither0: dither@1c007000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { }; + }; + }; }; dsi0: dsi@1c008000 {