| Message ID | 20250213112008.56394-4-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | MediaTek MT8195/MT8395 Display Controller Graph | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 41dc34837b02..7184dc99296c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -172,6 +172,32 @@ &cpu7 { cpu-supply = <&mt6315_6_vbuck1>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { }; + }; + }; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>;
This board can use a MIPI-DSI panel on the DSI0 connector: in preparation for adding an overlay for the Radxa Display 8HD, add a pipeline connecting VDOSYS0 components to DSI0. This pipeline remains disabled by default, as it is expected to be enabled only by a devicetree overlay that declares the actual DSI panel node, completing the graph. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)