From patchwork Sat Feb 15 10:06:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 13976021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7466AC021A0 for ; Sat, 15 Feb 2025 10:10:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wwUQ1gG+zU9mZ9mhGyEm41TVXi67wZbR+prnRoQw8Sc=; b=Tk32JGS53MwuDkuCTulolh+SYc cE0YBzN5+NHfMYeQjtFutpEpxKp9wVx+sfxw/lVjAMRsntyr0blJDTL/6rnX64lDf4wPDF9eqFw4b POaqheXxhLogfzJIHZxYecJxYbtOhPdqq4899j+p2QTCj7nJzRS+tSzcSx0ZcZddgDHn6leXQ5dVy 44h/qCNoIT/nPvn8QFwuJDrGTGgvuzwpkGnk65KFLa/xafy0PB5nwmtqfnoiemHRKKzIIuSZSF0Y4 fCoK/Tg5cLjrZdmb1aKO6ayp2QvwfZoz74t+8NJ47DZE0k7C1oteaWAK3Z7U9VNbZA+Hh2y6Skdwl MwJbAoxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tjF8N-0000000HPpg-2IBs; Sat, 15 Feb 2025 10:10:51 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tjF48-0000000HPCi-02Gs; Sat, 15 Feb 2025 10:06:29 +0000 X-UUID: 81e1258eeb8411ef9048ed6ed365623b-20250215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wwUQ1gG+zU9mZ9mhGyEm41TVXi67wZbR+prnRoQw8Sc=; b=FvgmFSCmihpHrvGxlg1ecI2CEIh8HaUBLtROxfrH1EnmDsMY7vPLXTKpWFgUtxnQ5G4op24PqfVPLbtMTfgqwq64qMbwKvOtJH1LjcZj8xAsPLVZMagH57FXwC56PiZ/auiWgxxWrMEWqyzFNa0hYxQiAX3WNpzYN1s95QCbcrs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:1324dd50-0bb9-4ea5-a145-92aa9d89fb4a,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:60aa074,CLOUDID:1d316988-f9ab-4ac1-951b-e3a689bed90c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 81e1258eeb8411ef9048ed6ed365623b-20250215 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1858017273; Sat, 15 Feb 2025 03:06:21 -0700 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Sat, 15 Feb 2025 18:06:19 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Sat, 15 Feb 2025 18:06:18 +0800 From: Chunfeng Yun To: Greg Kroah-Hartman , Rob Herring , AngeloGioacchino Del Regno CC: Chunfeng Yun , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Mathias Nyman , , , , , Subject: [PATCH v3 4/4] usb: mtu3: add support remote wakeup of mt8196 Date: Sat, 15 Feb 2025 18:06:14 +0800 Message-ID: <20250215100615.808-4-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250215100615.808-1-chunfeng.yun@mediatek.com> References: <20250215100615.808-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250215_020628_050078_9F8BC7A7 X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org There are three USB controllers on mt8196, each controller's wakeup control is different, add some specific versions for them. Signed-off-by: Chunfeng Yun Reviewed-by: AngeloGioacchino Del Regno --- v3: add the ommitted third dual-role controller suggested by Angelo v2: add wakeup for dual-role controllers --- drivers/usb/mtu3/mtu3_host.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c index 7c657ea2dabd..8138b3f3096a 100644 --- a/drivers/usb/mtu3/mtu3_host.c +++ b/drivers/usb/mtu3/mtu3_host.c @@ -46,6 +46,14 @@ #define WC1_IS_P_95 BIT(12) #define WC1_IS_EN_P0_95 BIT(6) +/* mt8196 */ +#define PERI_WK_CTRL0_8196 0x08 +#define WC0_IS_EN_P0_96 BIT(0) +#define WC0_IS_EN_P1_96 BIT(7) + +#define PERI_WK_CTRL1_8196 0x10 +#define WC1_IS_EN_P2_96 BIT(0) + /* mt2712 etc */ #define PERI_SSUSB_SPM_CTRL 0x0 #define SSC_IP_SLEEP_EN BIT(4) @@ -59,6 +67,9 @@ enum ssusb_uwk_vers { SSUSB_UWK_V1_3, /* mt8195 IP0 */ SSUSB_UWK_V1_5 = 105, /* mt8195 IP2 */ SSUSB_UWK_V1_6, /* mt8195 IP3 */ + SSUSB_UWK_V1_7, /* mt8196 IP0 */ + SSUSB_UWK_V1_8, /* mt8196 IP1 */ + SSUSB_UWK_V1_9, /* mt8196 IP2 */ }; /* @@ -100,6 +111,21 @@ static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable) msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0; break; + case SSUSB_UWK_V1_7: + reg = ssusb->uwk_reg_base + PERI_WK_CTRL0_8196; + msk = WC0_IS_EN_P0_96; + val = enable ? msk : 0; + break; + case SSUSB_UWK_V1_8: + reg = ssusb->uwk_reg_base + PERI_WK_CTRL0_8196; + msk = WC0_IS_EN_P1_96; + val = enable ? msk : 0; + break; + case SSUSB_UWK_V1_9: + reg = ssusb->uwk_reg_base + PERI_WK_CTRL1_8196; + msk = WC1_IS_EN_P2_96; + val = enable ? msk : 0; + break; case SSUSB_UWK_V2: reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL; msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;