@@ -249,6 +249,7 @@
#define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
#define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
#define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
+#define MSDC_PB1_SINGLE_BURST BIT(16) /* RW */
#define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
#define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
@@ -485,6 +486,7 @@ struct msdc_host {
u32 src_clk_freq; /* source clock frequency */
unsigned char timing;
bool vqmmc_enabled;
+ bool disable_single_burst;
u32 latch_ck;
u32 hs400_ds_delay;
u32 hs400_ds_dly3;
@@ -1874,6 +1876,10 @@ static void msdc_init_hw(struct msdc_host *host)
writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
+ if (host->disable_single_burst)
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT1,
+ MSDC_PB1_SINGLE_BURST);
+
if (host->dev_comp->stop_clk_fix) {
if (host->dev_comp->stop_dly_sel)
sdr_set_field(host->base + MSDC_PATCH_BIT1,
@@ -2820,6 +2826,10 @@ static void msdc_of_property_parse(struct platform_device *pdev,
host->cqhci = true;
else
host->cqhci = false;
+
+ host->disable_single_burst =
+ of_property_read_bool(pdev->dev.of_node,
+ "mediatek,disable-single-burst");
}
static int msdc_of_clock_parse(struct platform_device *pdev,
Add support to disable 'single' burst type if the bus type is AXI. Since the AMBA within some of the legacy and new designed MSDC IP is AXI, this switch is necessary. The burst type is not IC-specific, but host-specific. So we use a devicetree property 'mediatek,disable-single-burst' to switch burst type for specific MSDC host. Signed-off-by: Axe Yang <axe.yang@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 10 ++++++++++ 1 file changed, 10 insertions(+)