diff mbox series

[net-next,4/8] net: phy: realtek: disable SGMII in-band AN for 2.5G PHYs

Message ID 574c9703523af5643af0623144db3aa385635e84.1683756691.git.daniel@makrotopia.org (mailing list archive)
State New, archived
Headers show
Series Improvements for RealTek 2.5G Ethernet PHYs | expand

Commit Message

Daniel Golle May 10, 2023, 10:58 p.m. UTC 
MAC drivers don't use SGMII in-band autonegotiation unless told to do so
in device tree using 'managed = "in-band-status"'. When using MDIO to
access a PHY, in-band-status is unneeded as we have link-status via
MDIO. Switch off SGMII in-band autonegotiation using magic values.

Reported-by: Chen Minqiang <ptpt52@gmail.com>
Reported-by: Chukun Pan <amadeus@jmu.edu.cn>
Reported-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
Tested-by: Yevhen Kolomeiko <jarvis2709@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
 drivers/net/phy/realtek.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 0cf7846c9812..acadb6f0057b 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -666,7 +666,7 @@  static int rtl822x_get_features(struct phy_device *phydev)
 
 static int rtl822x_config_aneg(struct phy_device *phydev)
 {
-	int ret = 0;
+	int val, ret = 0;
 
 	if (phydev->autoneg == AUTONEG_ENABLE) {
 		u16 adv2500 = 0;
@@ -681,6 +681,19 @@  static int rtl822x_config_aneg(struct phy_device *phydev)
 			return ret;
 	}
 
+	/* MACs using phylink assume SGMII in-band status is not used.
+	 * Keep things as they are for MACs not using phylink such as
+	 * RealTek PCIe chips which come with built-in PHYs
+	 */
+	if (phydev->phylink) {
+		/* Disable SGMII AN */
+		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7588, 0x2);
+		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7589, 0x71d0);
+		phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587, 0x3);
+		phy_read_mmd_poll_timeout(phydev, RTL8221B_MMD_SERDES_CTRL, 0x7587,
+					  val, !(val & BIT(0)), 500, 100000, false);
+	}
+
 	return __genphy_config_aneg(phydev, ret);
 }