| Message ID | Y1iF2slvSblf6bYK@makrotopia.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | pwm: mediatek: always use bus clock for PWM on MT7622 | expand |
Il 26/10/22 02:56, Daniel Golle ha scritto: > According to MT7622 Reference Manual for Development Board v1.0 the PWM > unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register > at offset 0x210 just like other modern MediaTek ARM64 SoCs. > And also MT7622 sets that register to 0x00000001 on reset which is > described as 'Select 26M fix CLK as BCLK' in the datasheet. > Hence set has_ck_26m_sel to true also for MT7622 which results in the > driver writing 0 to the PWM_CK_26M_SEL register which is described as > 'Select bus CLK as BCLK'. > > Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock") > Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Fri, Oct 28, 2022 at 10:39:31AM +0200, AngeloGioacchino Del Regno wrote: > Il 26/10/22 02:56, Daniel Golle ha scritto: > > According to MT7622 Reference Manual for Development Board v1.0 the PWM > > unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register > > at offset 0x210 just like other modern MediaTek ARM64 SoCs. > > And also MT7622 sets that register to 0x00000001 on reset which is > > described as 'Select 26M fix CLK as BCLK' in the datasheet. > > Hence set has_ck_26m_sel to true also for MT7622 which results in the > > driver writing 0 to the PWM_CK_26M_SEL register which is described as > > 'Select bus CLK as BCLK'. > > > > Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock") > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Best regards Uwe
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 2219cba033e348..5b5eeaff35da67 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -296,7 +296,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = { static const struct pwm_mediatek_of_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, - .has_ck_26m_sel = false, + .has_ck_26m_sel = true, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = {
According to MT7622 Reference Manual for Development Board v1.0 the PWM unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register at offset 0x210 just like other modern MediaTek ARM64 SoCs. And also MT7622 sets that register to 0x00000001 on reset which is described as 'Select 26M fix CLK as BCLK' in the datasheet. Hence set has_ck_26m_sel to true also for MT7622 which results in the driver writing 0 to the PWM_CK_26M_SEL register which is described as 'Select bus CLK as BCLK'. Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock") Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- drivers/pwm/pwm-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)