| Message ID | YcjepQ2fmkPZ2+pE@makrotopia.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access | expand |
> + if (phy_register & MII_ADDR_C45) { > + u8 dev_num = (phy_register >> 16) & 0x1f; > + u16 reg = (u16)(phy_register & 0xffff); Hi Daniel You can use the helpers mdio_phy_id_is_c45() mdio_phy_id_prtad() mdio_phy_id_devad() Andrew
On Sun, Dec 26, 2021 at 10:51:08PM +0100, Andrew Lunn wrote: > > + if (phy_register & MII_ADDR_C45) { > > + u8 dev_num = (phy_register >> 16) & 0x1f; > > + u16 reg = (u16)(phy_register & 0xffff); > > Hi Daniel > > You can use the helpers > > mdio_phy_id_is_c45() > mdio_phy_id_prtad() > mdio_phy_id_devad() Before someone makes a mistake with this... no, don't use these. These are for the userspace MII ioctl API, not for drivers. The MII ioctl API passes the prtad and devad via the PHY ID field, and is decoded by the above macros. The internal API passes the prtad as the PHY ID and merges the devad into the register address. The C45 register address can be extracted by masking with MII_REGADDR_C45_MASK. The C45 devad can be extracted by shifting right by MII_DEVADDR_C45_SHIFT and masking 5 bits. We don't have helpers for this.
On Sun, Dec 26, 2021 at 09:57:04PM +0000, Russell King (Oracle) wrote: > On Sun, Dec 26, 2021 at 10:51:08PM +0100, Andrew Lunn wrote: > > > + if (phy_register & MII_ADDR_C45) { > > > + u8 dev_num = (phy_register >> 16) & 0x1f; > > > + u16 reg = (u16)(phy_register & 0xffff); > > > > Hi Daniel > > > > You can use the helpers > > > > mdio_phy_id_is_c45() > > mdio_phy_id_prtad() > > mdio_phy_id_devad() > > Before someone makes a mistake with this... no, don't use these. These > are for the userspace MII ioctl API, not for drivers. Ah, Sorry. Thanks Russell, i got this wrong. I though there was some helpers for this, and happened to land on bnxt_hwrm_port_phy_read(), without checking what it was actually used for. > The C45 register address can be extracted by masking with > MII_REGADDR_C45_MASK. The C45 devad can be extracted by shifting right > by MII_DEVADDR_C45_SHIFT and masking 5 bits. We don't have helpers for > this. Maybe we should have helpers. Andrew
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index bcb91b01e69f5..9f896a90a4c4c 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -102,10 +102,30 @@ static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, write_data &= 0xffff; - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | - (phy_register << PHY_IAC_REG_SHIFT) | - (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, - MTK_PHY_IAC); + if (phy_register & MII_ADDR_C45) { + u8 dev_num = (phy_register >> 16) & 0x1f; + u16 reg = (u16)(phy_register & 0xffff); + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT) | + reg, + MTK_PHY_IAC); + + if (mtk_mdio_busy_wait(eth)) + return 0xffff; + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT) | + write_data, + MTK_PHY_IAC); + } else { + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | + (phy_register << PHY_IAC_REG_SHIFT) | + (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, + MTK_PHY_IAC); + } if (mtk_mdio_busy_wait(eth)) return -1; @@ -120,10 +140,29 @@ static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) if (mtk_mdio_busy_wait(eth)) return 0xffff; - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | - (phy_reg << PHY_IAC_REG_SHIFT) | - (phy_addr << PHY_IAC_ADDR_SHIFT), - MTK_PHY_IAC); + if (phy_reg & MII_ADDR_C45) { + u8 dev_num = (phy_reg >> 16) & 0x1f; + u16 reg = (u16)(phy_reg & 0xffff); + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT) | + reg, + MTK_PHY_IAC); + + if (mtk_mdio_busy_wait(eth)) + return 0xffff; + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT), + MTK_PHY_IAC); + } else { + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | + (phy_reg << PHY_IAC_REG_SHIFT) | + (phy_addr << PHY_IAC_ADDR_SHIFT), + MTK_PHY_IAC); + } if (mtk_mdio_busy_wait(eth)) return 0xffff; @@ -497,6 +536,7 @@ static int mtk_mdio_init(struct mtk_eth *eth) eth->mii_bus->name = "mdio"; eth->mii_bus->read = mtk_mdio_read; eth->mii_bus->write = mtk_mdio_write; + eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; eth->mii_bus->priv = eth; eth->mii_bus->parent = eth->dev; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 5ef70dd8b49c6..b73d8adc9d24c 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -341,9 +341,12 @@ /* PHY Indirect Access Control registers */ #define MTK_PHY_IAC 0x10004 #define PHY_IAC_ACCESS BIT(31) +#define PHY_IAC_SET_ADDR 0 #define PHY_IAC_READ BIT(19) +#define PHY_IAC_READ_C45 (BIT(18) | BIT(19)) #define PHY_IAC_WRITE BIT(18) #define PHY_IAC_START BIT(16) +#define PHY_IAC_START_C45 0 #define PHY_IAC_ADDR_SHIFT 20 #define PHY_IAC_REG_SHIFT 25 #define PHY_IAC_TIMEOUT HZ
Implement read and write access to IEEE 802.3 Clause 45 Ethernet phy registers. Tested on the Ubiquiti UniFi 6 LR access point featuring MediaTek MT7622BV WiSoC with Aquantia AQR112C. Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 56 ++++++++++++++++++--- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++ 2 files changed, 51 insertions(+), 8 deletions(-)