From patchwork Thu Jun 27 08:12:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13713934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E99CC2BD09 for ; Thu, 27 Jun 2024 08:14:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xqDy56TPlvUI1OQOvZWVTp2JgrRKVA7+j8e6pz4qc+k=; b=H+VVZbm8IL8e1x6+eToYU0LIOp NF0ZqfVZdUJ7hQX+ctXq1m+8Abpar73fZ4K9hR6zF4x0mpChJcG/4oTcK6+d9aln9y1MAa+b3wg43 7Yu7xyyAYA+cSy1m/9dYGk2HgfGPBvFj/mOzxVHhxXZLyEN5KoGt1xsHeR7NGVB09fO4/a29Gn5YI xl/i3NM/JpSVY16slZD3sSkTojLTh4BkHSuDdMsEnNzIm3icGE7cktUlIxuhU/m+d7bgUWxZ2Nx+F 9E0inQW7Z8WKlsFapXyoCMnTo+V+s4KO9iRPkb60kD2dKntm7c5xSLIrepVP361XrM3BN6dOejiSI 8Q1CTYCw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMkGY-00000009hVc-29pu; Thu, 27 Jun 2024 08:14:02 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMkFn-00000009h80-1Mgp; Thu, 27 Jun 2024 08:13:17 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id D0AE4CE2D67; Thu, 27 Jun 2024 08:13:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F29BC2BD10; Thu, 27 Jun 2024 08:13:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719475991; bh=bctJ5X8cViosGAXVyA5Plj7UDdWbweJa/szjoCURJkc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F45GtDt1c7heeSvsahoIETmRGmlMdWJktstJhuW3WBxpyvRsXCWiUmD3jhlGtA7fX ph6PQ//jQ1AT5d2gYr4bxYHQ0FloVvCKPFxKkJ3nenknHUl3QllAleK41rGgvm7Aw6 NJJ08UnhDuapOm3u2Lx9+uMc0pxA+7mLYcst5AZ+TP1YNSFGAn1DZCreXmCTlMeRgG aXRuCXr1WH2GvZe6OIAr+1naFL4HTpufXPWnUCCeKURR8VMew5Q8A1Ieq5Kl/Jc4rF mNCsvr6sSgeKD6zIFAnBiYGCcNRsB58dDaF5J43L79B6Wah1917GCgFeDcuQEHb+vO NO0RXO98xPWOw== From: Lorenzo Bianconi To: linux-pci@vger.kernel.org Cc: ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi83@gmail.com, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, nbd@nbd.name, dd@embedd.com, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH v2 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support Date: Thu, 27 Jun 2024 10:12:14 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_011315_853638_C29241D7 X-CRM114-Status: GOOD ( 16.75 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3 PCIe controller driver. Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek-gen3.c | 96 ++++++++++++++++++++- 2 files changed, 96 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..3bd6c9430010 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -196,7 +196,7 @@ config PCIE_MEDIATEK config PCIE_MEDIATEK_GEN3 tristate "MediaTek Gen3 PCIe controller" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on PCI_MSI help Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 438a5222d986..af567b4355fa 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -15,6 +16,8 @@ #include #include #include +#include +#include #include #include #include @@ -29,6 +32,7 @@ #define PCI_CLASS(class) (class << 8) #define PCIE_RC_MODE BIT(0) +#define PCIE_EQ_PRESET_01_REF 0x100 #define PCIE_CFGNUM_REG 0x140 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) @@ -68,6 +72,7 @@ #define PCIE_MSI_SET_ENABLE_REG 0x190 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) +#define PCIE_PIPE4_PIE8_REG 0x338 #define PCIE_MSI_SET_BASE_REG 0xc00 #define PCIE_MSI_SET_OFFSET 0x10 #define PCIE_MSI_SET_STATUS_OFFSET 0x04 @@ -100,7 +105,17 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -#define MAX_NUM_PHY_RESETS 1 +/* EN7581 */ +#define PCIE_PEXTP_DIG_GLB44_P0_REG 0x10044 +#define PCIE_PEXTP_DIG_LN_RX30_P0_REG 0x15030 +#define PCIE_PEXTP_DIG_LN_RX30_P1_REG 0x15130 + +/* PCIe-PHY initialization delay in ms */ +#define PHY_INIT_TIME_MS 30 +/* PCIe reset line delay in ms */ +#define PCIE_RESET_TIME_MS 100 + +#define MAX_NUM_PHY_RESETS 3 struct mtk_gen3_pcie; @@ -847,6 +862,74 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) return 0; } +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) +{ + struct device *dev = pcie->dev; + int err; + + /* Wait for bulk assert completion in mtk_pcie_setup */ + mdelay(PCIE_RESET_TIME_MS); + + /* Setup Tx-Rx detect time */ + writel_relaxed(0x23020133, pcie->base + PCIE_PEXTP_DIG_GLB44_P0_REG); + /* Setup Rx AEQ training time */ + writel_relaxed(0x50500032, pcie->base + PCIE_PEXTP_DIG_LN_RX30_P0_REG); + writel_relaxed(0x50500032, pcie->base + PCIE_PEXTP_DIG_LN_RX30_P1_REG); + + err = phy_init(pcie->phy); + if (err) { + dev_err(dev, "failed to initialize PHY\n"); + return err; + } + mdelay(PHY_INIT_TIME_MS); + + err = phy_power_on(pcie->phy); + if (err) { + dev_err(dev, "failed to power on PHY\n"); + goto err_phy_on; + } + + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + if (err) { + dev_err(dev, "failed to deassert PHYs\n"); + goto err_phy_deassert; + } + mdelay(PCIE_RESET_TIME_MS); + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); + if (err) { + dev_err(dev, "failed to prepare clock\n"); + goto err_clk_prepare; + } + + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); + + err = clk_bulk_enable(pcie->num_clks, pcie->clks); + if (err) { + dev_err(dev, "failed to prepare clock\n"); + goto err_clk_enable; + } + + return 0; + +err_clk_enable: + clk_bulk_unprepare(pcie->num_clks, pcie->clks); +err_clk_prepare: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); +err_phy_deassert: + phy_power_off(pcie->phy); +err_phy_on: + phy_exit(pcie->phy); + + return err; +} + static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; @@ -1113,8 +1196,19 @@ static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = { }, }; +static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { + .power_up = mtk_pcie_en7581_power_up, + .phy_resets = { + .id[0] = "phy-lane0", + .id[1] = "phy-lane1", + .id[2] = "phy-lane2", + .num_resets = 3, + }, +}; + static const struct of_device_id mtk_pcie_of_match[] = { { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, + { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, {}, }; MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);