From patchwork Sun Jun 3 15:59:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdun Nihaal X-Patchwork-Id: 10445451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 70C3B603B4 for ; Sun, 3 Jun 2018 16:01:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D20F28A37 for ; Sun, 3 Jun 2018 16:01:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 51E5B28AEC; Sun, 3 Jun 2018 16:01:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, DKIM_VALID, FREEMAIL_FROM, MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D14C528A37 for ; Sun, 3 Jun 2018 16:01:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=9zBwhCmBC3kujuN3q6S1tQ31qe/96g9r/Dnu9igCMY8=; b=MwZHlUMUCBrNbowid5LrbLRjSR oEJmks44nvp0k/W7+cUDgHotivkJqtt+Kp9ZExJlF989mLNfRchfnpMAjKz2WJiBMtDgjWV0M3cuB AtVhDhIVLcZuxqmDFj5XmAk86T6p1ZTzXRhUCgoQOT/NFz+rr/llTHpzNZsrLWOmT7Bk8xj2IHPg3 zHV16kAjeZ20UcBk/U3LZLb6fYmW22hVpITl9g2OMBRCBP4NXpCTJZlwu3QKb6BcKqpS0roMcFALf PWA71wBdnqhIwNEuwNU1ilyLnBM+KPjvgN9zec6K+nFASUiA41D0ZR0pY4ityRE6NJGJ5WC3UX5RB xbiUcvJQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fPVS4-0000Bo-8i for patchwork-linux-mediatek@patchwork.kernel.org; Sun, 03 Jun 2018 16:01:52 +0000 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fPVRX-00089M-37; Sun, 03 Jun 2018 16:01:26 +0000 Received: by mail-pg0-x244.google.com with SMTP id 15-v6so13011037pge.2; Sun, 03 Jun 2018 09:01:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=TvK3sH+rAOE5nVBtiwebojqsTOFFcpPqfE8KOj32gdQ=; b=dseP0sCLGg+Z5tl/SyYcLlEqYCdSDAdx2pUZX6NEW5/k6y/w+fpwAyfWtMpfLGJB3K JE1KIbPoDC4PSQiKrUEixQRRjAdzxTKvCDbS8TBQVxomszM8odnYWJRBexyDCue+3VUa TFxXT4ATFaTJSQc+JNmDyW+fSwjPca7sDhG+ECInFOaB1wzrFpdHA5JHuIygWXAGQZRU 5BAdQf/RdhhI86Uk0nv3Ux9VCJnKsUE9ej0KaDys0X7724lq++N9JduFMS4Me5rXq3rd C1xJtZzYRn2Jof8IoH+w/wZJCmU+QwrFK7Cn3KlWyjPidQhSmn6hm0Gh8FDJS36zeKy6 Mp/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=TvK3sH+rAOE5nVBtiwebojqsTOFFcpPqfE8KOj32gdQ=; b=qVP4NKr/91+tt/x3Nt5AspsnCU3ATOsp9ZxTQT9ITNeabUOBNVvlrCF1XUnxDjXu9M UkFxIjBmYaYlqPrVbGwThm1GVSrOz/1lT+oRdL8IhOYH+CqtfXwpxiX0OiTJpoABZK8g 7ARhwH5tRq33IjvGi+6v6a+j5tD3WVBsCag+RZ7kdDvf3D7pe3xHOnyuRXrJvZq6JDcW 6cj0cpvjrm3uRvgfGzwNwOj6kxQ9IM0/AIBlex9aZZSc28EhSmYX1BZKoyy8wYs7JRaJ p8MQGgo14iUzelw99s3RitPTB50Q4J9fSbPZ0noiqqdkPxOW8dzaLOCAinhttV3H/xCe oeBw== X-Gm-Message-State: ALKqPwe6F4TtX+QxFZ43USAi9yX1Yw7CYj+lfin6B0v4+PoshWaU4T9t ZnH+nT12r4A32VY2uI6KiwA= X-Google-Smtp-Source: ADUXVKI/EJX/JP9apn4pWXXEF64xIEAWK3Se8p5ilqH4lo4Qwj2358QNLx7S8wbmzRBgZmzvn3XVag== X-Received: by 2002:a65:5288:: with SMTP id y8-v6mr14739204pgp.69.1528041668110; Sun, 03 Jun 2018 09:01:08 -0700 (PDT) Received: from nihaal-Latitude-E6410 ([157.50.194.246]) by smtp.gmail.com with ESMTPSA id m11-v6sm26589006pfj.25.2018.06.03.09.01.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Jun 2018 09:01:07 -0700 (PDT) From: Abdun Nihaal To: gregkh@linuxfoundation.org Subject: [PATCH 2/7] staging: mt7621-pci: remove trailing whitespace Date: Sun, 3 Jun 2018 21:29:59 +0530 Message-Id: X-Mailer: git-send-email 2.17.0 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180603_090119_148464_45D915B2 X-CRM114-Status: UNSURE ( 9.08 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, Abdun Nihaal , neil@brown.name, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This fixes the following checkpatch error: ERROR: trailing whitespace Signed-off-by: Abdun Nihaal --- drivers/staging/mt7621-pci/pci-mt7621.c | 32 ++++++++++++------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 44f1a592a7a5..fbcee58445b3 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -498,7 +498,7 @@ set_phy_for_ssc(void) printk("***** Xtal 40MHz *****\n"); } else { // 25MHz | 20MHz Xtal set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) - if (reg >= 6) { + if (reg >= 6) { printk("***** Xtal 25MHz *****\n"); set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) @@ -510,15 +510,15 @@ set_phy_for_ssc(void) } } set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN if(reg <= 5 && reg >= 3) { // 40MHz Xtal set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv } /* Enable PHY and disable force mode */ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable @@ -546,15 +546,15 @@ set_phy_for_ssc(void) } } set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN if(reg <= 5 && reg >= 3) { // 40MHz Xtal set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable - set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv } /* Enable PHY and disable force mode */ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable @@ -650,7 +650,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) RALINK_PCIE_CLK_GEN |= 0x80000000; mdelay(50); RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST); - + #if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/ *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA