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[83.47.240.79]) by smtp.gmail.com with ESMTPSA id l8sm4089610wrv.45.2019.03.29.22.50.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Mar 2019 22:50:40 -0700 (PDT) From: Sergio Paracuellos To: kishon@ti.com Cc: linux-kernel@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devicetree@vger.kernel.org, john@phrozen.org, linux-mips@vger.kernel.org, robh+dt@kernel.org, neil@brown.name Subject: [PATCH v2 0/2] MT7621 PCIe PHY Date: Sat, 30 Mar 2019 06:50:36 +0100 Message-Id: <20190330055038.18958-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This series adds support for the PCIe PHY found in the Mediatek MT7621 SoC. This is the first attempt to get feedback of what is missing in this driver to be promoted from staging. There is also a 'mt7621-pci' driver which is the controller part which is still in staging and is a client of this phy. Both drivers have been tested together in a gnubee1 board. Changes in v2: - Reorder patches to get bindings first in the series. - Don't use child nodes in the device tree. Use #phy-cells=1 instead. - Update driver code with new 'xlate' function for the new device tree. - Minor changes in driver's macros changing some spaces to tabs. Thanks in advance for your time. Best regards, Sergio Paracuellos Sergio Paracuellos (2): dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY phy: ralink: Add PHY driver for MT7621 PCIe PHY .../bindings/phy/mediatek,mt7621-pci-phy.txt | 28 ++ drivers/phy/ralink/Kconfig | 7 + drivers/phy/ralink/Makefile | 1 + drivers/phy/ralink/phy-mt7621-pci.c | 401 ++++++++++++++++++ 4 files changed, 437 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.txt create mode 100644 drivers/phy/ralink/phy-mt7621-pci.c