[0/2] Repair X1000E SoC L2 cache capacity detection.

Message

Zhou Yanjie Sept. 19, 2020, 12:44 p.m. UTC

The X1000E SoC has a 4-way L2 cache with a capacity of 128 KiB.
The current code cannot detect its correctly, which will cause
the CU1000-Neo board using the X1000E SoC to report that it
has found a 5-way 320KiB L2 cache at boot time. This series
of patches is to fix this problem.

周琰杰 (Zhou Yanjie) (2):
  MIPS: X1000E: Add X1000E system type.
  MIPS: Ingenic: Fix bugs when detecting X1000E's L2 cache.

 arch/mips/generic/board-ingenic.c | 3 +++
 arch/mips/include/asm/bootinfo.h  | 1 +
 arch/mips/mm/sc-mips.c            | 1 +
 3 files changed, 5 insertions(+)