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[83.57.27.10]) by smtp.gmail.com with ESMTPSA id y11sm14861976wru.0.2021.08.22.09.10.05 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Aug 2021 09:10:06 -0700 (PDT) From: Sergio Paracuellos To: tsbogend@alpha.franken.de Cc: bhelgaas@google.com, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, linux-mips@vger.kernel.org, linux-pci@vger.kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] MIPS: ralink: properly handle pci IO resources Date: Sun, 22 Aug 2021 18:10:02 +0200 Message-Id: <20210822161005.22467-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hi all, Defining PCI_IOBASE for MIPS ralink platform results in resource handling working but the addresses generated for IO access being wrong, because the iomap tries to ioremap it to a fixed virtual address (PCI_IOBASE), which can't work for KSEG1 addresses. To get it working this way, we would need to put PCI_IOBASE somewhere into KSEG2, which will create TLB entries for IO addresses, which most of the time isn't needed on MIPS because of access via KSEG1. Instead of doing that and taking into account that we need to get a valid IO address from 'pci_address_to_pio' and ralink platforms have IO addresses higher than 0xffff, the following approach will be preferred to get expected working behaviour from PCI core APIs and pci drivers working together: 1) Avoid to define PCI_IOBASE. 2) Set IO_SPACE_LIMIT to 0x1fffffff which is a valid range for this SoCs. 3) Return zero from 'pci_remap_iospace' if PCI_IOBASE is not defined. 3) Set ioport_resource end limit to this new IO_SPACE_LIMIT. Doing in this way we end up with a properly working PCI IO in ralink SoCs. These changes metioned above are in the three patches included in this series. Thanks in advance for your time and comments. Changes in v2 (only PATCH v2 2/3 afected): - Instead of avoid to call 'devm_pci_remap_iospace' fix 'pci_remap_iospace' to return zero for PCI_IOBASE not defined architectures. Bjorn, I don't know if I should add any kind of 'Fixes' tag for this or what is the way of handle this kind of changes inside the PCI tree. Thanks in advance for clarification. Sergio Paracuellos (3): MIPS: ralink: don't define PC_IOBASE but increase IO_SPACE_LIMIT PCI: fix 'pci_remap_iospace' for architectures with PCI_IOBASE not defined staging: mt7621-pci: set end limit for 'ioport_resource' arch/mips/include/asm/mach-ralink/spaces.h | 4 +--- drivers/pci/pci.c | 12 ++++++------ drivers/staging/mt7621-pci/pci-mt7621.c | 2 ++ 3 files changed, 9 insertions(+), 9 deletions(-)