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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id b187sm4811625wmd.33.2021.09.21.22.00.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Sep 2021 22:00:37 -0700 (PDT) From: Sergio Paracuellos To: linux-pci@vger.kernel.org Cc: lorenzo.pieralisi@arm.com, john@phrozen.org, devicetree@vger.kernel.org, tsbogend@alpha.franken.de, bhelgaas@google.com, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, linux-mips@vger.kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Date: Wed, 22 Sep 2021 07:00:32 +0200 Message-Id: <20210922050035.18162-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org MediaTek MT7621 PCIe subsys supports single Root complex (RC) with 3 Root Ports. Each Root Ports supports a Gen1 1-lane Link. Topology is as follows: MT7621 PCIe HOST Topology .-------. | | | CPU | | | '-------' | | | v .------------------. .-----------| HOST/PCI Bridge |------------. | '------------------' | Type1 BUS0 | | | Access v v v On Bus0 .-------------. .-------------. .-------------. | VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P | | BUS0 | | BUS0 | | BUS0 | | DEV0 | | DEV1 | | DEV2 | '-------------' '-------------' '-------------' Type0 | Type0 | Type0 | Access BUS1 | Access BUS2| Access BUS3| On Bus1 v On Bus2 v On Bus3 v .----------. .----------. .----------. | Device 0 | | Device 0 | | Device 0 | | Func 0 | | Func 0 | | Func 0 | '----------' '----------' '----------' This driver has been very long time in staging and I have been cleaning it from its first versions where there was code kaos and PCI_LEGACY support. Original code came probably from openWRT based on mediatek's SDK code. There is no documentation at all about the mt7621 PCI subsystem. I have been cleaning it targeting mt7621 SoC which is the one I use in my GNUBee PC1 board and HiLink HLK-MT7621A evaluation board. Now I think is clean enough to be moved into 'drivers/pci/controller'. This driver is mips/ralink architecture and need 'mips_cps_numiocu()' to properly configure iocu regions for mips. This driver also uses already mainlined pci phy driver located in 'drivers/phy/ralink/phy-mt7621-pci.c'. There are two instances of the phy being the first one dual ported for pci0 and pci1, and the second one not dual ported dedicated to pci2. Because of writing twice some phy registers of the dual-ported one sometimes become in not confident boot cycles we have to take care of this when device link is checked here in controller driver. We power on the dual ported-phy if there is something connected in pcie0 or pcie1. In the same manner we have to properly disable it only if nothing is connected in of both pcie0 and pcie1 slots. This changes are rebased on the top of staging-next branch of staging tree for a clean git mv since last changes are always in that tree. Since this a git mv as I was told to do, include link to the last code here [0]. Changes in v3: - Add Rob's Reviewed-by for the bindings. - Avoid custom 'of_pci_range_to_resource' in driver side since PCI core APIs has been changed to properly support this architecture. - Kconfig: - Change from 'bool' to 'tristate'. - Add phy's selection 'select PHY_MT7621_PCI'. - Move PCI_DRIVERS_GENERIC selection to 'arch/mips' since its mips internal stuff (change requested by Lorenzo in v2 review of this series). Changes in v2: - Make one commit moving driver directly from staging into 'drivers/pci/controllers' instead of two commits making one add and a later remove. - Update binding documentation moving 'clocks', 'resets' and 'phys' properties to child root bridge nodes. - Update code to properly be able to use new bindings. - Kconfig: add || (MIPS && COMPILE_TEST). - Use {read/write}_relaxed versions. - Use 'PCI_BASE_ADDRESS_0' instead of a custom definition. - Avoid to set 'PCI_COMMAND_MASTER' and re-do functions 'mt7621_pcie_enable_ports' and 'mt7621_pcie_enable_port'. Thanks in advance for your time. Best regards, Sergio Paracuellos [0]: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git/tree/drivers/staging/mt7621-pci/pci-mt7621.c?h=staging-testing Sergio Paracuellos (3): dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver MAINTAINERS: add myself as maintainer of the MT7621 PCI controller driver .../bindings/pci/mediatek,mt7621-pci.yaml | 142 ++++++++++++++++++ MAINTAINERS | 6 + arch/mips/ralink/Kconfig | 3 +- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + .../controller}/pci-mt7621.c | 0 drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/mt7621-pci/Kconfig | 8 - drivers/staging/mt7621-pci/Makefile | 2 - drivers/staging/mt7621-pci/TODO | 4 - .../mt7621-pci/mediatek,mt7621-pci.txt | 104 ------------- 12 files changed, 159 insertions(+), 122 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%) delete mode 100644 drivers/staging/mt7621-pci/Kconfig delete mode 100644 drivers/staging/mt7621-pci/Makefile delete mode 100644 drivers/staging/mt7621-pci/TODO delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt