[v3,0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

Message

Serge Semin May 3, 2022, 8:57 p.m. UTC

This patchset is an initial one in the series created in the framework
of my Baikal-T1 PCIe/eDMA-related work:

[1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
Link: https://lore.kernel.org/linux-pci/[e-mail]/
[2: In-progress v1] PCI: dwc: Various fixes and cleanups
Link: https://lore.kernel.org/linux-pci/[e-mail]/
[3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
Link: https://lore.kernel.org/linux-pci/[e-mail]/
[4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
Link: https://lore.kernel.org/linux-pci/[e-mail]/

Since some of the patches in the later patchsets depend on the
modifications introduced here, @Lorenzo could you please merge this series
through your PCIe subsystem repo? After getting all the required ack'es of
course.

Short summary regarding this patchset. A few more modifications are
introduced here to finally finish the Baikal-T1 CCU unit support up and
prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
all it turned out I specified wrong DW xGMAC PTP reference clock divider
in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
joint xGMAC Ref and PTP clock instead of having them separately defined.
The SoC manual describes these clocks as separate fixed clock wrappers.
Finally in order to close the SoC clock/reset support up we need to add
the DDR and PCIe interfaces reset controls support. It's done in two
steps. First I've moved the reset-controls-related code into a dedicated
module. Then the DDR/PCIe reset-control functionality is added.

Link: https://lore.kernel.org/linux-pci/[e-mail]/
Changelog v2:
- Resubmit the series with adding @Philipp to the list of the recipients.

Link: https://lore.kernel.org/linux-pci/[e-mail]/
Changelog v3:
- Rebased from v5.17 onto v5.18-rc3.
- No comments. Just resend the series.

Signed-off-by: Serge Semin <[e-mail]>
Cc: Alexey Malahov <[e-mail]>
Cc: Pavel Parkhomenko <[e-mail]>
Cc: Rob Herring <[e-mail]>
Cc: "Krzysztof Wilczyński" <[e-mail]>
Cc: Bjorn Helgaas <[e-mail]>
Cc: Thomas Bogendoerfer <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]
Cc: [e-mail]

Serge Semin (4):
  clk: baikal-t1: Fix invalid xGMAC PTP clock divider
  clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
  clk: baikal-t1: Move reset-controls code into a dedicated module
  clk: baikal-t1: Add DDR/PCIe directly controlled resets support

 drivers/clk/baikal-t1/Kconfig       |  12 +-
 drivers/clk/baikal-t1/Makefile      |   1 +
 drivers/clk/baikal-t1/ccu-div.c     |   1 +
 drivers/clk/baikal-t1/ccu-div.h     |   6 +
 drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
 drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
 drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
 include/dt-bindings/reset/bt1-ccu.h |   9 +
 8 files changed, 482 insertions(+), 86 deletions(-)
 create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
 create mode 100644 drivers/clk/baikal-t1/ccu-rst.h

Comments

Serge Semin May 12, 2022, 12:11 a.m. UTC | #1

On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> This patchset is an initial one in the series created in the framework
> of my Baikal-T1 PCIe/eDMA-related work:
> 
> [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> 
> Since some of the patches in the later patchsets depend on the
> modifications introduced here, @Lorenzo could you please merge this series
> through your PCIe subsystem repo? After getting all the required ack'es of
> course.
> 
> Short summary regarding this patchset. A few more modifications are
> introduced here to finally finish the Baikal-T1 CCU unit support up and
> prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> all it turned out I specified wrong DW xGMAC PTP reference clock divider
> in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> joint xGMAC Ref and PTP clock instead of having them separately defined.
> The SoC manual describes these clocks as separate fixed clock wrappers.
> Finally in order to close the SoC clock/reset support up we need to add
> the DDR and PCIe interfaces reset controls support. It's done in two
> steps. First I've moved the reset-controls-related code into a dedicated
> module. Then the DDR/PCIe reset-control functionality is added.
> 
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> Changelog v2:
> - Resubmit the series with adding @Philipp to the list of the recipients.
> 
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> Changelog v3:
> - Rebased from v5.17 onto v5.18-rc3.
> - No comments. Just resend the series.

No comments for more than a week. There were no comments in v1 and v2
either. Please at least ack or merge in the series. It would be very
appreciated to merge it in through one repo with the rest of the
patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?

-Sergey

> 
> Signed-off-by: Serge Semin <[e-mail]>
> Cc: Alexey Malahov <[e-mail]>
> Cc: Pavel Parkhomenko <[e-mail]>
> Cc: Rob Herring <[e-mail]>
> Cc: "Krzysztof Wilczyński" <[e-mail]>
> Cc: Bjorn Helgaas <[e-mail]>
> Cc: Thomas Bogendoerfer <[e-mail]>
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> 
> Serge Semin (4):
>   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
>   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
>   clk: baikal-t1: Move reset-controls code into a dedicated module
>   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> 
>  drivers/clk/baikal-t1/Kconfig       |  12 +-
>  drivers/clk/baikal-t1/Makefile      |   1 +
>  drivers/clk/baikal-t1/ccu-div.c     |   1 +
>  drivers/clk/baikal-t1/ccu-div.h     |   6 +
>  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
>  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
>  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
>  include/dt-bindings/reset/bt1-ccu.h |   9 +
>  8 files changed, 482 insertions(+), 86 deletions(-)
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> 
> -- 
> 2.35.1
>

Lorenzo Pieralisi May 12, 2022, 3:27 p.m. UTC | #2

On Thu, May 12, 2022 at 03:11:56AM +0300, Serge Semin wrote:
> On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> > This patchset is an initial one in the series created in the framework
> > of my Baikal-T1 PCIe/eDMA-related work:
> > 
> > [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > 
> > Since some of the patches in the later patchsets depend on the
> > modifications introduced here, @Lorenzo could you please merge this series
> > through your PCIe subsystem repo? After getting all the required ack'es of
> > course.
> > 
> > Short summary regarding this patchset. A few more modifications are
> > introduced here to finally finish the Baikal-T1 CCU unit support up and
> > prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> > all it turned out I specified wrong DW xGMAC PTP reference clock divider
> > in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> > joint xGMAC Ref and PTP clock instead of having them separately defined.
> > The SoC manual describes these clocks as separate fixed clock wrappers.
> > Finally in order to close the SoC clock/reset support up we need to add
> > the DDR and PCIe interfaces reset controls support. It's done in two
> > steps. First I've moved the reset-controls-related code into a dedicated
> > module. Then the DDR/PCIe reset-control functionality is added.
> > 
> > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > Changelog v2:
> > - Resubmit the series with adding @Philipp to the list of the recipients.
> > 
> > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > Changelog v3:
> > - Rebased from v5.17 onto v5.18-rc3.
> > - No comments. Just resend the series.
> 
> No comments for more than a week. There were no comments in v1 and v2
> either. Please at least ack or merge in the series. It would be very
> appreciated to merge it in through one repo with the rest of the
> patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?

Hi Sergey,

these changes affect the clock tree and have to be reviewed and merged
by the respective maintainers if they think the changes can be accepted.

I don't see any reason why we should, if ACK'ed, take them in the PCI
tree, this series does not apply changes to the PCI tree at all and you
don't need it as a base for future to-be-merged PCI patches either.

So in short, this series has to go through the usual clock tree review
process.

Thanks,
Lorenzo

> -Sergey
> 
> > 
> > Signed-off-by: Serge Semin <[e-mail]>
> > Cc: Alexey Malahov <[e-mail]>
> > Cc: Pavel Parkhomenko <[e-mail]>
> > Cc: Rob Herring <[e-mail]>
> > Cc: "Krzysztof Wilczyński" <[e-mail]>
> > Cc: Bjorn Helgaas <[e-mail]>
> > Cc: Thomas Bogendoerfer <[e-mail]>
> > Cc: [e-mail]
> > Cc: [e-mail]
> > Cc: [e-mail]
> > Cc: [e-mail]
> > 
> > Serge Semin (4):
> >   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
> >   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
> >   clk: baikal-t1: Move reset-controls code into a dedicated module
> >   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> > 
> >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> >  drivers/clk/baikal-t1/Makefile      |   1 +
> >  drivers/clk/baikal-t1/ccu-div.c     |   1 +
> >  drivers/clk/baikal-t1/ccu-div.h     |   6 +
> >  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
> >  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
> >  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
> >  include/dt-bindings/reset/bt1-ccu.h |   9 +
> >  8 files changed, 482 insertions(+), 86 deletions(-)
> >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
> >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> > 
> > -- 
> > 2.35.1
> >

Manivannan Sadhasivam May 12, 2022, 5:11 p.m. UTC | #3

On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> On Thu, May 12, 2022 at 03:11:56AM +0300, Serge Semin wrote:
> > On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> > > This patchset is an initial one in the series created in the framework
> > > of my Baikal-T1 PCIe/eDMA-related work:
> > > 
> > > [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > 
> > > Since some of the patches in the later patchsets depend on the
> > > modifications introduced here, @Lorenzo could you please merge this series
> > > through your PCIe subsystem repo? After getting all the required ack'es of
> > > course.
> > > 
> > > Short summary regarding this patchset. A few more modifications are
> > > introduced here to finally finish the Baikal-T1 CCU unit support up and
> > > prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> > > all it turned out I specified wrong DW xGMAC PTP reference clock divider
> > > in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> > > joint xGMAC Ref and PTP clock instead of having them separately defined.
> > > The SoC manual describes these clocks as separate fixed clock wrappers.
> > > Finally in order to close the SoC clock/reset support up we need to add
> > > the DDR and PCIe interfaces reset controls support. It's done in two
> > > steps. First I've moved the reset-controls-related code into a dedicated
> > > module. Then the DDR/PCIe reset-control functionality is added.
> > > 
> > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > Changelog v2:
> > > - Resubmit the series with adding @Philipp to the list of the recipients.
> > > 
> > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > Changelog v3:
> > > - Rebased from v5.17 onto v5.18-rc3.
> > > - No comments. Just resend the series.
> > 
> > No comments for more than a week. There were no comments in v1 and v2
> > either. Please at least ack or merge in the series. It would be very
> > appreciated to merge it in through one repo with the rest of the
> > patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?
> 
> Hi Sergey,
> 
> these changes affect the clock tree and have to be reviewed and merged
> by the respective maintainers if they think the changes can be accepted.
> 
> I don't see any reason why we should, if ACK'ed, take them in the PCI
> tree, this series does not apply changes to the PCI tree at all and you
> don't need it as a base for future to-be-merged PCI patches either.
> 
> So in short, this series has to go through the usual clock tree review
> process.
> 

Yes, Stephen should be the one taking these patches through the clk tree. Also,
there is no need to club both pci and clk patches in a single tree. That's
usually done for patches with build dependencies, but here there are none.

Thanks,
Mani

> Thanks,
> Lorenzo
> 
> > -Sergey
> > 
> > > 
> > > Signed-off-by: Serge Semin <[e-mail]>
> > > Cc: Alexey Malahov <[e-mail]>
> > > Cc: Pavel Parkhomenko <[e-mail]>
> > > Cc: Rob Herring <[e-mail]>
> > > Cc: "Krzysztof Wilczyński" <[e-mail]>
> > > Cc: Bjorn Helgaas <[e-mail]>
> > > Cc: Thomas Bogendoerfer <[e-mail]>
> > > Cc: [e-mail]
> > > Cc: [e-mail]
> > > Cc: [e-mail]
> > > Cc: [e-mail]
> > > 
> > > Serge Semin (4):
> > >   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
> > >   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
> > >   clk: baikal-t1: Move reset-controls code into a dedicated module
> > >   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> > > 
> > >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> > >  drivers/clk/baikal-t1/Makefile      |   1 +
> > >  drivers/clk/baikal-t1/ccu-div.c     |   1 +
> > >  drivers/clk/baikal-t1/ccu-div.h     |   6 +
> > >  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
> > >  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
> > >  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
> > >  include/dt-bindings/reset/bt1-ccu.h |   9 +
> > >  8 files changed, 482 insertions(+), 86 deletions(-)
> > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
> > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> > > 
> > > -- 
> > > 2.35.1
> > >

Serge Semin May 12, 2022, 9:14 p.m. UTC | #4

On Thu, May 12, 2022 at 10:41:50PM +0530, Manivannan Sadhasivam wrote:
> On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> > On Thu, May 12, 2022 at 03:11:56AM +0300, Serge Semin wrote:
> > > On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> > > > This patchset is an initial one in the series created in the framework
> > > > of my Baikal-T1 PCIe/eDMA-related work:
> > > > 
> > > > [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> > > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > > [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> > > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > > [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> > > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > > [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> > > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > > 
> > > > Since some of the patches in the later patchsets depend on the
> > > > modifications introduced here, @Lorenzo could you please merge this series
> > > > through your PCIe subsystem repo? After getting all the required ack'es of
> > > > course.
> > > > 
> > > > Short summary regarding this patchset. A few more modifications are
> > > > introduced here to finally finish the Baikal-T1 CCU unit support up and
> > > > prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> > > > all it turned out I specified wrong DW xGMAC PTP reference clock divider
> > > > in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> > > > joint xGMAC Ref and PTP clock instead of having them separately defined.
> > > > The SoC manual describes these clocks as separate fixed clock wrappers.
> > > > Finally in order to close the SoC clock/reset support up we need to add
> > > > the DDR and PCIe interfaces reset controls support. It's done in two
> > > > steps. First I've moved the reset-controls-related code into a dedicated
> > > > module. Then the DDR/PCIe reset-control functionality is added.
> > > > 
> > > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > > Changelog v2:
> > > > - Resubmit the series with adding @Philipp to the list of the recipients.
> > > > 
> > > > Link: https://lore.kernel.org/linux-pci/[e-mail]/
> > > > Changelog v3:
> > > > - Rebased from v5.17 onto v5.18-rc3.
> > > > - No comments. Just resend the series.
> > > 
> > > No comments for more than a week. There were no comments in v1 and v2
> > > either. Please at least ack or merge in the series. It would be very
> > > appreciated to merge it in through one repo with the rest of the
> > > patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?
> > 

Hello Lorenzo, Manivannan

> > Hi Sergey,
> > 
> > these changes affect the clock tree and have to be reviewed and merged
> > by the respective maintainers if they think the changes can be accepted.
> > 
> > I don't see any reason why we should, if ACK'ed, take them in the PCI
> > tree, this series does not apply changes to the PCI tree at all and you
> > don't need it as a base for future to-be-merged PCI patches either.
> > 
> > So in short, this series has to go through the usual clock tree review
> > process.
> > 

I do know the normal procedure. But if patches concern different
subsystems but for some reason inter-depended somehow it's ok to merge
them in via a single repo. In my case the platform clock driver has
been updated in a way so to support the reset-controls utilized in the
PCIe driver altered in another patchset. So I didn't want to leave the
kernel not working in the framework of my platform on any git hash
state. That's why I asked to merge the patchsets in via the same repo.
The kernel would be still buildable though.

> 
> Yes, Stephen should be the one taking these patches through the clk tree. Also,
> there is no need to club both pci and clk patches in a single tree. That's
> usually done for patches with build dependencies, but here there are none.

Well, I didn't expect to have my patchsets review to be that delayed.
Now seeing Lorenzo is going to review only DW PCIe fixes and cleanups
after which will be gone for two more months I have to admit that my
plan of getting the changes accepted in 5.19 won't come true. Really
I thought of any subsystem but not of PCIe/DMA that review procedure
would last that long.

-Sergey

> 
> Thanks,
> Mani
> 
> > Thanks,
> > Lorenzo
> > 
> > > -Sergey
> > > 
> > > > 
> > > > Signed-off-by: Serge Semin <[e-mail]>
> > > > Cc: Alexey Malahov <[e-mail]>
> > > > Cc: Pavel Parkhomenko <[e-mail]>
> > > > Cc: Rob Herring <[e-mail]>
> > > > Cc: "Krzysztof Wilczyński" <[e-mail]>
> > > > Cc: Bjorn Helgaas <[e-mail]>
> > > > Cc: Thomas Bogendoerfer <[e-mail]>
> > > > Cc: [e-mail]
> > > > Cc: [e-mail]
> > > > Cc: [e-mail]
> > > > Cc: [e-mail]
> > > > 
> > > > Serge Semin (4):
> > > >   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
> > > >   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
> > > >   clk: baikal-t1: Move reset-controls code into a dedicated module
> > > >   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> > > > 
> > > >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> > > >  drivers/clk/baikal-t1/Makefile      |   1 +
> > > >  drivers/clk/baikal-t1/ccu-div.c     |   1 +
> > > >  drivers/clk/baikal-t1/ccu-div.h     |   6 +
> > > >  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
> > > >  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
> > > >  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
> > > >  include/dt-bindings/reset/bt1-ccu.h |   9 +
> > > >  8 files changed, 482 insertions(+), 86 deletions(-)
> > > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
> > > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> > > > 
> > > > -- 
> > > > 2.35.1
> > > > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்

Serge Semin May 13, 2022, 11:44 a.m. UTC | #5

Hello Stephen, Michael

The series has been here for about two months with no comments. Seeing
the dependent patches won't be merged in before the next merge window,
could you please merge this series in through your repo?

-Sergey

On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> This patchset is an initial one in the series created in the framework
> of my Baikal-T1 PCIe/eDMA-related work:
> 
> [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> 
> Since some of the patches in the later patchsets depend on the
> modifications introduced here, @Lorenzo could you please merge this series
> through your PCIe subsystem repo? After getting all the required ack'es of
> course.
> 
> Short summary regarding this patchset. A few more modifications are
> introduced here to finally finish the Baikal-T1 CCU unit support up and
> prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> all it turned out I specified wrong DW xGMAC PTP reference clock divider
> in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> joint xGMAC Ref and PTP clock instead of having them separately defined.
> The SoC manual describes these clocks as separate fixed clock wrappers.
> Finally in order to close the SoC clock/reset support up we need to add
> the DDR and PCIe interfaces reset controls support. It's done in two
> steps. First I've moved the reset-controls-related code into a dedicated
> module. Then the DDR/PCIe reset-control functionality is added.
> 
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> Changelog v2:
> - Resubmit the series with adding @Philipp to the list of the recipients.
> 
> Link: https://lore.kernel.org/linux-pci/[e-mail]/
> Changelog v3:
> - Rebased from v5.17 onto v5.18-rc3.
> - No comments. Just resend the series.
> 
> Signed-off-by: Serge Semin <[e-mail]>
> Cc: Alexey Malahov <[e-mail]>
> Cc: Pavel Parkhomenko <[e-mail]>
> Cc: Rob Herring <[e-mail]>
> Cc: "Krzysztof Wilczyński" <[e-mail]>
> Cc: Bjorn Helgaas <[e-mail]>
> Cc: Thomas Bogendoerfer <[e-mail]>
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> Cc: [e-mail]
> 
> Serge Semin (4):
>   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
>   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
>   clk: baikal-t1: Move reset-controls code into a dedicated module
>   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> 
>  drivers/clk/baikal-t1/Kconfig       |  12 +-
>  drivers/clk/baikal-t1/Makefile      |   1 +
>  drivers/clk/baikal-t1/ccu-div.c     |   1 +
>  drivers/clk/baikal-t1/ccu-div.h     |   6 +
>  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
>  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
>  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
>  include/dt-bindings/reset/bt1-ccu.h |   9 +
>  8 files changed, 482 insertions(+), 86 deletions(-)
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> 
> -- 
> 2.35.1
>

Stephen Boyd May 17, 2022, 7:40 a.m. UTC | #6

Quoting Serge Semin (2022-05-12 14:14:31)
> On Thu, May 12, 2022 at 10:41:50PM +0530, Manivannan Sadhasivam wrote:
> > On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> > > So in short, this series has to go through the usual clock tree review
> > > process.
> > > 
> 
> I do know the normal procedure. But if patches concern different
> subsystems but for some reason inter-depended somehow it's ok to merge
> them in via a single repo. In my case the platform clock driver has
> been updated in a way so to support the reset-controls utilized in the
> PCIe driver altered in another patchset. So I didn't want to leave the
> kernel not working in the framework of my platform on any git hash
> state. That's why I asked to merge the patchsets in via the same repo.
> The kernel would be still buildable though.
> 

Is it going to be broken if I merge the clk patches through clk tree?
Has it ever worked? Does the kernel still boot, just PCIe fails if the
patches are applied?

Serge Semin May 17, 2022, 10:05 a.m. UTC | #7

On Tue, May 17, 2022 at 12:40:18AM -0700, Stephen Boyd wrote:
> Quoting Serge Semin (2022-05-12 14:14:31)
> > On Thu, May 12, 2022 at 10:41:50PM +0530, Manivannan Sadhasivam wrote:
> > > On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> > > > So in short, this series has to go through the usual clock tree review
> > > > process.
> > > > 
> > 
> > I do know the normal procedure. But if patches concern different
> > subsystems but for some reason inter-depended somehow it's ok to merge
> > them in via a single repo. In my case the platform clock driver has
> > been updated in a way so to support the reset-controls utilized in the
> > PCIe driver altered in another patchset. So I didn't want to leave the
> > kernel not working in the framework of my platform on any git hash
> > state. That's why I asked to merge the patchsets in via the same repo.
> > The kernel would be still buildable though.
> > 
> 

> Is it going to be broken if I merge the clk patches through clk tree?

No. It won't be broken.

> Has it ever worked?

It has and is working well except some minor fixes provided in this
petchset:
[PATCH v3 1/4] clk: baikal-t1: Fix invalid xGMAC PTP clock divider
[PATCH v3 2/4] clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent

> Does the kernel still boot, just PCIe fails if the
> patches are applied?

Yes, the kernel will be bootable. There won't be any problem if the patches
in this series are applied because it is self-consistent. As I
said in the cover letter there is an implicit dependency of another series
"[PATCH v2 00/17] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support"
(https://lore.kernel.org/linux-pci/[e-mail]/T/#me3c5c248adad9760702b545bd4bacd89d5f8a2bd)
from this one. In particular the functionality implemented in the
patch
"[PATCH v2 17/17] PCI: dwc: Add Baikal-T1 PCIe controller support"
(https://lore.kernel.org/linux-pci/[e-mail]/T/#m219e11c38c4ab8db0c2520c4050366d641598600)
depends on the patches 3 and 4 of this patchset. But the
dependency is implicit hidden under the DT clock/reset bindings layer.
The Baikal-T1 PCIe platform driver will just fail to probe the host
controller device if this series isn't applied. So the clock/reset
patchset can be freely merged in via the clk tree especially seeing
the PCIe Host/EP subsystem maintainer is going to be AFK from
Wednesday and my series will sadly but likely hang up in limbo for a
while.

-Sergey