| Message ID | 20230321050034.1431379-1-sergio.paracuellos@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | mips: ralink: add complete clock and reset driver for mtmips SoCs | expand |
On Tue, Mar 21, 2023 at 6:00 AM Sergio Paracuellos <sergio.paracuellos@gmail.com> wrote: > > Hi all! > > This patchset is a big effort to properly implement a clock and reset > driver for old ralink SoCs. This allow to properly define clocks in > device tree and avoid to use fixed-clocks directly from 'arch/mips/ralink' > architecture directory code. > > Device tree 'sysc' node will be both clock and reset provider using > 'clock-cells' and 'reset-cells' properties. > > The ralink SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, > RT3352, RT3883, RT5350, MT7620, MT7628 and MT7688. Mostly the code in > this new driver has been extracted from 'arch/mips/ralink' and cleanly > put using kernel clock and reset driver APIs. The clock plans for this > SoCs only talks about relation between CPU frequency and BUS frequency. > This relation is different depending on the particular SoC. CPU clock is > derived from XTAL frequencies. > > Depending on the SoC we have the following frequencies: > * RT2880 SoC: > - XTAL: 40 MHz. > - CPU: 250, 266, 280 or 300 MHz. > - BUS: CPU / 2 MHz. > * RT3050, RT3052, RT3350: > - XTAL: 40 MHz. > - CPU: 320 or 384 MHz. > - BUS: CPU / 3 MHz. > * RT3352: > - XTAL: 40 MHz. > - CPU: 384 or 400 MHz. > - BUS: CPU / 3 MHz. > - PERIPH: 40 MHz. > * RT3383: > - XTAL: 40 MHz. > - CPU: 250, 384, 480 or 500 MHz. > - BUS: Depends on RAM Type and CPU: > + RAM DDR2: 125. ELSE 83 MHz. > + RAM DDR2: 128. ELSE 96 MHz. > + RAM DDR2: 160. ELSE 120 MHz. > + RAM DDR2: 166. ELSE 125 MHz. > * RT5350: > - XTAL: 40 MHz. > - CPU: 300, 320 or 360 MHz. > - BUS: CPU / 3, CPU / 4, CPU / 3 MHz. > - PERIPH: 40 MHz. > * MT7628 and MT7688: > - XTAL: 20 MHz or 40 MHz. > - CPU: 575 or 580 MHz. > - BUS: CPU / 3. > - PCMI2S: 480 MHz. > - PERIPH: 40 MHz. > * MT7620: > - XTAL: 20 MHz or 40 MHz. > - PLL: XTAL, 480, 600 MHz. > - CPU: depends on PLL and some mult and dividers. > - BUS: depends on PLL and some mult and dividers. > - PERIPH: 40 or XTAL MHz. > > MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of > register reads and predividers. To derive CPU and BUS frequencies in the > MT7620 SoC 'mt7620_calc_rate()' helper is used. > In the case XTAL can have different frequencies and we need a different > clock frequency for peripherals 'periph' clock in introduced. > The rest of the peripherals present in the SoC just follow their parent > frequencies. > > I am using 'mtmips' inside for ralink clock driver. This is aligned with > pinctrl series recently merged through pinctrl git tree [0]. > > Changes have been compile tested for: > - RT2880 > - RT3883 > - MT7620 > > Changes have been properly tested in RT5350 SoC based board (ALL5003 board) > resulting in a working platform. > > Dts files for these SoCs in-tree except MT7621 are incomplete. We are > planning to align with openWRT files at some point and add extra needed > changes. Hence I am not touching them at all in these series. If this is > a problem, please let me know and I will update them. > > Talking about merging this series I'd like all of the patches going through > the MIPS tree if possible. > > Thanks in advance for your time. > > Best regards, > Sergio Paracuellos > > Changes in v2: > - Address bindings documentation changes pointed out by Krzysztof: > + Rename the file into 'mediatek,mtmips-sysc.yaml'. > + Redo commit subject and log message. > + Order compatibles alphabetically. > + Redo bindings description taking into account this is a system > controller node which provides both clocks and resets to the world. > + Drop label from example. > + Use 'syscon' as node name in example. > + Drop no sense 'ralink,rt2880-reset' compatible string > - Squash patches 6 and 7 together as pointed out by Stephen Boyd. Gentle ping on this series :-) Thanks, Sergio Paracuellos > > Previous series: > v1: https://lore.kernel.org/linux-clk/20230320161823.1424278-1-sergio.paracuellos@gmail.com/T/#t > > [0]: https://lore.kernel.org/linux-gpio/e9e6ad87-2db5-9767-ff39-64a302b06185@arinc9.com/T/#t > > Sergio Paracuellos (9): > dt-bindings: clock: add mtmips SoCs system controller > clk: ralink: add clock and reset driver for MTMIPS SoCs > mips: ralink: rt288x: remove clock related code > mips: ralink: rt305x: remove clock related code > mips: ralink: rt3883: remove clock related code > mips: ralink: mt7620: remove clock related code > mips: ralink: remove reset related code > mips: ralink: get cpu rate from new driver code > MAINTAINERS: add Mediatek MTMIPS Clock maintainer > > .../bindings/clock/mediatek,mtmips-sysc.yaml | 65 ++ > MAINTAINERS | 6 + > arch/mips/include/asm/mach-ralink/mt7620.h | 35 - > arch/mips/include/asm/mach-ralink/rt288x.h | 10 - > arch/mips/include/asm/mach-ralink/rt305x.h | 21 - > arch/mips/include/asm/mach-ralink/rt3883.h | 8 - > arch/mips/ralink/clk.c | 26 +- > arch/mips/ralink/common.h | 5 - > arch/mips/ralink/mt7620.c | 226 ---- > arch/mips/ralink/of.c | 4 - > arch/mips/ralink/reset.c | 61 -- > arch/mips/ralink/rt288x.c | 31 - > arch/mips/ralink/rt305x.c | 78 -- > arch/mips/ralink/rt3883.c | 44 - > drivers/clk/ralink/Kconfig | 7 + > drivers/clk/ralink/Makefile | 1 + > drivers/clk/ralink/clk-mtmips.c | 985 ++++++++++++++++++ > 17 files changed, 1083 insertions(+), 530 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml > create mode 100644 drivers/clk/ralink/clk-mtmips.c > > -- > 2.25.1 >
Quoting Sergio Paracuellos (2023-04-13 01:44:56) > > Gentle ping on this series :-) Please trim replies. I had marked the whole series as superseded because of the first patch discussions. I reviewed the clk driver now. In general, use the fixed rate and fixed factor basic clk types. Don't change hardware in recalc_rate().
On Thu, Apr 13, 2023 at 8:56 PM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Sergio Paracuellos (2023-04-13 01:44:56) > > > > Gentle ping on this series :-) > > Please trim replies. I had marked the whole series as superseded because > of the first patch discussions. I reviewed the clk driver now. In > general, use the fixed rate and fixed factor basic clk types. Don't > change hardware in recalc_rate(). Thanks, Stephen. I was expecting an answer in my request of Reviewed-by of the bindings after the discussion about the first patch between Arinc and Rob before resending anything [0]. I will reply to your review comments shortly. Thanks, Sergio Paracuellos [0]: https://lore.kernel.org/linux-mips/d20a8910675be9acab3b2f4ac123fbf3.sboyd@kernel.org/T/#m6ae224c084b5b482ccfe0cfd0d936fb9ce1354b0
Hi all! This patchset is a big effort to properly implement a clock and reset driver for old ralink SoCs. This allow to properly define clocks in device tree and avoid to use fixed-clocks directly from 'arch/mips/ralink' architecture directory code. Device tree 'sysc' node will be both clock and reset provider using 'clock-cells' and 'reset-cells' properties. The ralink SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883, RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has been extracted from 'arch/mips/ralink' and cleanly put using kernel clock and reset driver APIs. The clock plans for this SoCs only talks about relation between CPU frequency and BUS frequency. This relation is different depending on the particular SoC. CPU clock is derived from XTAL frequencies. Depending on the SoC we have the following frequencies: * RT2880 SoC: - XTAL: 40 MHz. - CPU: 250, 266, 280 or 300 MHz. - BUS: CPU / 2 MHz. * RT3050, RT3052, RT3350: - XTAL: 40 MHz. - CPU: 320 or 384 MHz. - BUS: CPU / 3 MHz. * RT3352: - XTAL: 40 MHz. - CPU: 384 or 400 MHz. - BUS: CPU / 3 MHz. - PERIPH: 40 MHz. * RT3383: - XTAL: 40 MHz. - CPU: 250, 384, 480 or 500 MHz. - BUS: Depends on RAM Type and CPU: + RAM DDR2: 125. ELSE 83 MHz. + RAM DDR2: 128. ELSE 96 MHz. + RAM DDR2: 160. ELSE 120 MHz. + RAM DDR2: 166. ELSE 125 MHz. * RT5350: - XTAL: 40 MHz. - CPU: 300, 320 or 360 MHz. - BUS: CPU / 3, CPU / 4, CPU / 3 MHz. - PERIPH: 40 MHz. * MT7628 and MT7688: - XTAL: 20 MHz or 40 MHz. - CPU: 575 or 580 MHz. - BUS: CPU / 3. - PCMI2S: 480 MHz. - PERIPH: 40 MHz. * MT7620: - XTAL: 20 MHz or 40 MHz. - PLL: XTAL, 480, 600 MHz. - CPU: depends on PLL and some mult and dividers. - BUS: depends on PLL and some mult and dividers. - PERIPH: 40 or XTAL MHz. MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of register reads and predividers. To derive CPU and BUS frequencies in the MT7620 SoC 'mt7620_calc_rate()' helper is used. In the case XTAL can have different frequencies and we need a different clock frequency for peripherals 'periph' clock in introduced. The rest of the peripherals present in the SoC just follow their parent frequencies. I am using 'mtmips' inside for ralink clock driver. This is aligned with pinctrl series recently merged through pinctrl git tree [0]. Changes have been compile tested for: - RT2880 - RT3883 - MT7620 Changes have been properly tested in RT5350 SoC based board (ALL5003 board) resulting in a working platform. Dts files for these SoCs in-tree except MT7621 are incomplete. We are planning to align with openWRT files at some point and add extra needed changes. Hence I am not touching them at all in these series. If this is a problem, please let me know and I will update them. Talking about merging this series I'd like all of the patches going through the MIPS tree if possible. Thanks in advance for your time. Best regards, Sergio Paracuellos Changes in v2: - Address bindings documentation changes pointed out by Krzysztof: + Rename the file into 'mediatek,mtmips-sysc.yaml'. + Redo commit subject and log message. + Order compatibles alphabetically. + Redo bindings description taking into account this is a system controller node which provides both clocks and resets to the world. + Drop label from example. + Use 'syscon' as node name in example. + Drop no sense 'ralink,rt2880-reset' compatible string - Squash patches 6 and 7 together as pointed out by Stephen Boyd. Previous series: v1: https://lore.kernel.org/linux-clk/20230320161823.1424278-1-sergio.paracuellos@gmail.com/T/#t [0]: https://lore.kernel.org/linux-gpio/e9e6ad87-2db5-9767-ff39-64a302b06185@arinc9.com/T/#t Sergio Paracuellos (9): dt-bindings: clock: add mtmips SoCs system controller clk: ralink: add clock and reset driver for MTMIPS SoCs mips: ralink: rt288x: remove clock related code mips: ralink: rt305x: remove clock related code mips: ralink: rt3883: remove clock related code mips: ralink: mt7620: remove clock related code mips: ralink: remove reset related code mips: ralink: get cpu rate from new driver code MAINTAINERS: add Mediatek MTMIPS Clock maintainer .../bindings/clock/mediatek,mtmips-sysc.yaml | 65 ++ MAINTAINERS | 6 + arch/mips/include/asm/mach-ralink/mt7620.h | 35 - arch/mips/include/asm/mach-ralink/rt288x.h | 10 - arch/mips/include/asm/mach-ralink/rt305x.h | 21 - arch/mips/include/asm/mach-ralink/rt3883.h | 8 - arch/mips/ralink/clk.c | 26 +- arch/mips/ralink/common.h | 5 - arch/mips/ralink/mt7620.c | 226 ---- arch/mips/ralink/of.c | 4 - arch/mips/ralink/reset.c | 61 -- arch/mips/ralink/rt288x.c | 31 - arch/mips/ralink/rt305x.c | 78 -- arch/mips/ralink/rt3883.c | 44 - drivers/clk/ralink/Kconfig | 7 + drivers/clk/ralink/Makefile | 1 + drivers/clk/ralink/clk-mtmips.c | 985 ++++++++++++++++++ 17 files changed, 1083 insertions(+), 530 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml create mode 100644 drivers/clk/ralink/clk-mtmips.c