[RFC,v2,0/2] irqchip/loongson-eiointc: Add multiple interrupt pin routing support

Message

Bibo Mao Aug. 28, 2024, 7:06 a.m. UTC

There are four times about EIOINTC_REG_ISR register group access in
eiointc irq handler, in order to get all irq status about 256 interrupt
vectors. It causes four times VM-exits since eiointc register are
software emulated, here multiple interrupt pin routing is introduced
and each 64 interrupt vector is routed to one interrupt pin.

With this method, there will be only on one EIOINTC_REG_ISR register
group acces in irq handler, it will reduce VM-exits.

---
v1 ... v2:
  1. Add different route_info handler as eiointc interrupt handler
     parameter, so that irq handler can read corresponding ISR
  2. Call function set_csr_ecfg() to enable cpu interrupt pin in eiointc
     driver inside.

---
Bibo Mao (2):
  irqchip/loongson-eiointc: Route interrupt parsed from acpi table
  irqchip/loongson-eiointc: Add multiple interrupt pin routing support

 drivers/irqchip/irq-loongson-eiointc.c | 83 +++++++++++++++++++++++---
 1 file changed, 75 insertions(+), 8 deletions(-)


base-commit: 3ec3f5fc4a91e389ea56b111a73d97ffc94f19c6