[v4,00/10] MIPS: IPI Improvements

Message

Jiaxun Yang Sept. 7, 2024, 11:48 a.m. UTC

Hi all,

This series improved general handling to MIPS IPI interrupts, made
IPI numbers scalable, and switch to IPI-MUX for all GERNERIC_IPI
users on mux.

It is a prerequisite for enabling IRQ_WORK for MIPS.

It has been tested on MIPS Boston I6500, malta CoreFPGA3 47K MT/
interAPtiv MPF, Loongson-2K, Cavium CN7130 (EdgeRouter 4), and an
unannounced interaptiv UP MT platform with EIC.

I don't really know broadcom platforms and SGI platforms well so
changes to those platforms are kept minimal (no functional change).

Please review.
Thanks

Signed-off-by: Jiaxun Yang <[e-mail]>
---
Changes in v4:
- irqchip commit message and code style fixes (tglx)
- Link to v3: https://lore.kernel.org/r/[e-mail]

Changes in v3:
- Fix build errors reported by kernel test bot
- Rebasing to current next
- Link to v2: https://lore.kernel.org/r/[e-mail]

Changes in v2:
- Build warning fixes
- Massage commit messages
- Link to v1: https://lore.kernel.org/r/[e-mail]

---
Jiaxun Yang (10):
      MIPS: smp: Make IPI interrupts scalable
      MIPS: smp: Manage IPI interrupts as percpu_devid interrupts
      MIPS: smp: Provide platform IPI virq & domain hooks
      MIPS: Move mips_smp_ipi_init call after prepare_cpus
      MIPS: smp: Implement IPI stats
      irqchip/irq-mips-gic: Switch to ipi_mux
      MIPS: Implement get_mips_sw_int hook
      MIPS: GIC: Implement get_sw_int hook
      irqchip/irq-mips-cpu: Rework software IRQ handling flow
      MIPS: smp-mt: Rework IPI functions

 arch/mips/Kconfig                     |   2 +
 arch/mips/cavium-octeon/smp.c         | 111 ++++++-----------
 arch/mips/fw/arc/init.c               |   1 -
 arch/mips/generic/irq.c               |  15 +++
 arch/mips/include/asm/ipi.h           |  71 +++++++++++
 arch/mips/include/asm/irq.h           |   1 +
 arch/mips/include/asm/irq_cpu.h       |   3 +
 arch/mips/include/asm/mips-gic.h      |  10 ++
 arch/mips/include/asm/octeon/octeon.h |   2 +
 arch/mips/include/asm/smp-ops.h       |   8 +-
 arch/mips/include/asm/smp.h           |  41 +++----
 arch/mips/kernel/irq.c                |  21 ++++
 arch/mips/kernel/smp-bmips.c          |  43 ++++---
 arch/mips/kernel/smp-cps.c            |   2 +
 arch/mips/kernel/smp-mt.c             |  70 +++++++++++
 arch/mips/kernel/smp.c                | 213 ++++++++++++++++++++-------------
 arch/mips/loongson64/smp.c            |  24 ++--
 arch/mips/mm/c-octeon.c               |   3 +-
 arch/mips/sgi-ip27/ip27-smp.c         |  15 ++-
 arch/mips/sgi-ip30/ip30-smp.c         |  15 ++-
 arch/mips/sibyte/bcm1480/smp.c        |  19 +--
 arch/mips/sibyte/sb1250/smp.c         |  13 +-
 drivers/irqchip/Kconfig               |   2 +-
 drivers/irqchip/irq-mips-cpu.c        | 191 +++++++++---------------------
 drivers/irqchip/irq-mips-gic.c        | 217 +++++++++++++---------------------
 25 files changed, 590 insertions(+), 523 deletions(-)
---
base-commit: 61c01d2e181adfba02fe09764f9fca1de2be0dbe
change-id: 20240616-b4-mips-ipi-improvements-f8c86b1dc677

Best regards,

Comments

Jiaxun Yang Sept. 7, 2024, 11:53 a.m. UTC | #1

在2024年9月7日九月 下午12:48，Jiaxun Yang写道：
> Hi all,
>
> This series improved general handling to MIPS IPI interrupts, made
> IPI numbers scalable, and switch to IPI-MUX for all GERNERIC_IPI
> users on mux.
>
> It is a prerequisite for enabling IRQ_WORK for MIPS.
>
> It has been tested on MIPS Boston I6500, malta CoreFPGA3 47K MT/
> interAPtiv MPF, Loongson-2K, Cavium CN7130 (EdgeRouter 4), and an
> unannounced interaptiv UP MT platform with EIC.
>
> I don't really know broadcom platforms and SGI platforms well so
> changes to those platforms are kept minimal (no functional change).

Oops please ignore this reversion, I made a mistake on local version management.

Will resend, sorry for the noise.

Thanks