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AJvYcCVjV+He0WFAGiphCVXKyugMLN/SIhKyaUh5tAjEI3asDM5+RDzuGgGPD+/YhwfXDaqw4m7tkSph0qSB@vger.kernel.org, AJvYcCW+yAuNvnkscNILdfyad21/VWCaB2vpl8FDfaRfMLoXq/3r9Gq49Wnaj+rfCpy6v34y4x4x6o5r3x4Axlic@vger.kernel.org, AJvYcCX2CEidoKOf5powxV7Ys/KC5etrYZOypzlBC6G5mLVZQ7Aa61Me6uFay4S7O4PkqztjYDQCbGH6dpYC0Q==@vger.kernel.org X-Gm-Message-State: AOJu0YxVDqylu1kJvlpRyrIjnDBkXZhFKF5QYue1afHzYMVqQ0OM1RNy UpKnru2QjPQSm6izgzfPLVeaD6u6nzT0cfYV6ghqCsMLu4gecdF7 X-Google-Smtp-Source: AGHT+IE4wZOrxBGDczr6W+gTxkO6LW+u/+0VFfkJ/WAb0XKbP4UU4zd224H+MxBcDhYNo+LAhLsCBw== X-Received: by 2002:a2e:2403:0:b0:2fb:357a:be4d with SMTP id 38308e7fff4ca-2fcbe0a35aemr48417031fa.43.1730138378952; Mon, 28 Oct 2024 10:59:38 -0700 (PDT) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1dfbdfe2sm396990766b.36.2024.10.28.10.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2024 10:59:38 -0700 (PDT) From: Aleksandar Rikalo To: Thomas Bogendoerfer Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Kondratiev , Gregory CLEMENT , Theo Lebrun , Arnd Bergmann , devicetree@vger.kernel.org, Djordje Todorovic , Chao-ying Fu , Daniel Lezcano , Geert Uytterhoeven , Greg Ungerer , Hauke Mehrtens , Ilya Lipnitskiy , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Marc Zyngier , Paul Burton , Peter Zijlstra , Serge Semin , Tiezhu Yang , Aleksandar Rikalo Subject: [PATCH v8 00/13] MIPS: Support I6500 multi-cluster configuration Date: Mon, 28 Oct 2024 18:59:22 +0100 Message-Id: <20241028175935.51250-1-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu. Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and 1 cluster/4 VPU configurations. v8: - irqchip: mips-gic: Handle case with cluster without CPU cores. - Add Tested-by: Gregory CLEMENT for the entire series. - Re-base onto the master branch, with no functionality impact. v7: - Add fixes for specific CM3.5 which is used in EyeQ6H SoCs, suggested by Gregory Clement. - Re-base onto the master branch, with no functionality impact. v6: - Re-base onto the master branch, with no functionality impact. - Correct the issue reported by the kernel test robot. v5: - Drop FDC related changes (patches 12, 13, and 14). - Apply changes suggested by Thomas Gleixner (patches 3 and 4). - Add #include to patch 1, suggested by Thomas Bogendoerfer. - Add Reviewed-by: Philippe Mathieu-Daudé for the patch 08/11. - Add Tested-by: Serge Semin for the entire series. - Correct some commit messages. v4: - Re-base onto the master branch, with no functionality impact. - Refactor MIPS FDC driver in the context of multicluster support. v3: - Add Reviewed-by: Jiaxun Yang for the patch 02/12. - Add the changes requested by Marc Zyngier for the 3/12 patch. - Remove the patch 11/12 (a consequence of a discussion between Jiaxun Yang and Marc Zyngier. - Re-base onto the master branch, with no functionality impact. v2: - Apply correct Signed-off-by to avoid confusion. Chao-ying Fu (1): irqchip/mips-gic: Setup defaults in each cluster Gregory CLEMENT (4): dt-bindings: mips: cpu: Add property for broken HCI information MIPS: CPS: Support broken HCI for multicluster MIPS: mobileye: dts: eyeq6h: Enable cluster support irqchip: mips-gic: Handle case with cluster without CPU cores Paul Burton (8): irqchip/mips-gic: Introduce for_each_online_cpu_gic() irqchip/mips-gic: Support multi-cluster in for_each_online_cpu_gic() irqchip/mips-gic: Multi-cluster support clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource clocksource: mips-gic-timer: Enable counter when CPUs start MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core MIPS: CPS: Introduce struct cluster_boot_config MIPS: CPS: Boot CPUs in secondary clusters .../devicetree/bindings/mips/cpus.yaml | 6 + arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 1 + arch/mips/include/asm/mips-cm.h | 18 ++ arch/mips/include/asm/smp-cps.h | 7 +- arch/mips/kernel/asm-offsets.c | 3 + arch/mips/kernel/cps-vec.S | 19 +- arch/mips/kernel/mips-cm.c | 4 +- arch/mips/kernel/pm-cps.c | 35 +- arch/mips/kernel/smp-cps.c | 305 +++++++++++++++--- drivers/clocksource/mips-gic-timer.c | 45 ++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-mips-gic.c | 269 ++++++++++++--- 12 files changed, 599 insertions(+), 114 deletions(-) Tested-by: Jiaxun Yang # Single cluster I6500