[v2,0/2] serial, Malta: Fixes to make the CBUS UART work big-endian

Message ID	alpine.DEB.2.21.2106260509300.37803@angie.orcam.me.uk (mailing list archive)
Headers	show Return-Path: <linux-mips-owner@kernel.org> Date: Sat, 26 Jun 2021 06:10:57 +0200 (CEST) From: "Maciej W. Rozycki" <macro@orcam.me.uk> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Thomas Bogendoerfer <tsbogend@alpha.franken.de> cc: linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 0/2] serial, Malta: Fixes to make the CBUS UART work big-endian Message-ID: <alpine.DEB.2.21.2106260509300.37803@angie.orcam.me.uk> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk
Series	serial, Malta: Fixes to make the CBUS UART work big-endian \| expand [v2,0/2] serial, Malta: Fixes to make the CBUS UART work big-endian [v2,1/2] serial: 8250: Mask out floating 16/32-bit bus bits [v2,2/2] MIPS: Malta: Do not byte-swap accesses to the CBUS UART

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alpine.DEB.2.21.2106260509300.37803@angie.orcam.me.uk (mailing list archive)

Headers

Date: Sat, 26 Jun 2021 06:10:57 +0200 (CEST)
From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
cc: linux-serial@vger.kernel.org, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: [PATCH v2 0/2] serial, Malta: Fixes to make the CBUS UART work
 big-endian
Message-ID: <alpine.DEB.2.21.2106260509300.37803@angie.orcam.me.uk>
User-Agent: Alpine 2.21 (DEB 202 2017-01-01)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Precedence: bulk

Series

serial, Malta: Fixes to make the CBUS UART work big-endian | expand

Message

Maciej W. Rozycki June 26, 2021, 4:10 a.m. UTC

Hi,

 Earlier this year I noticed the CBUS UART, a discrete TI16C550C part 
wired directly to the system controller's device bus and supposed to come 
up as ttyS2 in addition to ttyS0 and ttyS1 ports from a Super I/O device 
behind the PCI southbridge, is not recognised with my MIPS Malta board 
booting big-endian.

 I got to the bottom of the problem now and as it turns out we have two 
long-standing bugs causing it, one in generic 8250 code and another in 
Malta platform code, and this has never worked in the big-endian mode.  

 Here's v2 of the series, addressing minor issues with 1/2 pointed out in 
the review.

 Please apply.

  Maciej