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[2001:1ae9:ff1:f191:359a:8d64:e90a:f663]) by smtp.gmail.com with ESMTPSA id f204sm4986394wme.18.2019.06.08.13.48.28 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 13:48:29 -0700 (PDT) From: petrcvekcz@gmail.com X-Google-Original-From: petrcvekcz.gmail.com To: hauke@hauke-m.de, john@phrozen.org Cc: Petr Cvek , linux-mips@vger.kernel.org, openwrt-devel@lists.openwrt.org, pakahmar@hotmail.com Subject: [PATCH v1 0/7] MIPS: lantiq: irq: Various fixes, add SMP support Date: Sat, 8 Jun 2019 22:48:03 +0200 Message-Id: X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Petr Cvek Hi, While hacking with my modem in openwrt I've found in the lantiq vrx268 SoC there is only a support for the processes SMP and not for interrupt routing. After some looking into vendors released source codes (probably intel UGW) and by observing SoC's memory map I've found out there is a second interrupt controller (ICU) for the second VPE. The last patch of this series adds support for it. The code is different from intel UGW's set affinity function, where the interrupt line gets enabled (switched) to the second ICU. Instead only the cpumask gets changed in my set affinity. The change will be written into the hardware after the next irq enable call. This was changed because of stability reasons in the high irq load of the SoC. The first part of the series are more or less cosmetic changes of long names, different types and few fixed warnings from checkpatch. There is a fix in part 5, where I've found the missing bitfield clear before ORing with a new value. The SMP in part 7 changes devicetree definition for a register regions of the ICU. Previously, there was a region for a single IM (a mask/unmask/ enable/... set for 32 interrupts). Now it is the whole ICU. It match more the hardware layout. There is no compatibility issue in vanilla, only openwrt was affected by these devicetrees. Also in the UGW's ltq_enable_irq(), there was a status bit reset before the actual IRQ line enable. It was marked as "Bug fix for fake interrupt". The code seems to work without it (vanilla and new SMP), but I've made an assert if this bit is set before the actual enable. The assert reported these IRQ sources: 22:00004000 spi_rx (only when SPI is accessed) 63:00800000 mei_cpe (permanent 1s) 112:00000100 asc_tx But the code seems to run anyway I didn't include the status bit reset part. The SMP has an algorithm taken from MIPS loongson64's ht_irqdispatch(). Every IRQ enable the line get routed to the other VPE (constrained by cpumask set in the irq_set_affinity function). This can be effectivelly disabled in the userspace by constraining the cpumask set to a single VPE or by commenting out the AUTO_AFFINITY_ROTATION macro definition (the code will then prefer the first VPE from the cpumask). The default affinity during the boot is the first VPE. The code was tested in nosmp configuration on TPLink W9980B in openwrt tree (patched kernel v4.14). The lantiq devices other than vrx268 were not tested. Discussion on openwrt related parts for lantiq ICU SMP is here (devicetrees, things not in the vanilla kernel, RFC versions of the patch): https://patchwork.ozlabs.org/patch/1100832/ Petr Cvek (7): MIPS: lantiq: Move macro directly to iomem function MIPS: lantiq: Change variables to the same type as the source MIPS: lantiq: Fix attributes of of_device_id structure MIPS: lantiq: Remove unused macros MIPS: lantiq: Fix bitfield masking MIPS: lantiq: Shorten register names, remove unused macros MIPS: lantiq: Add SMP support for lantiq interrupt controller arch/mips/lantiq/irq.c | 202 ++++++++++++++++++++++++++++++----------- 1 file changed, 151 insertions(+), 51 deletions(-)