| Message ID | 1589898923-60048-6-git-send-email-zhouyanjie@wanyeetech.com (mailing list archive) |
|---|---|
| State | Deferred |
| Headers | show |
| Series | [v8,1/6] MIPS: JZ4780: Introduce SMP support. | expand |
On Tue, May 19, 2020 at 10:35:21PM +0800, 周琰杰 (Zhou Yanjie) wrote: > Document the available properties for the SoC root node and the > CPU nodes of the devicetree for the Ingenic XBurst SoCs. > > Tested-by: H. Nikolaus Schaller <hns@goldelico.com> > Tested-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > --- > > Notes: > v1->v2: > Change the two Document from txt to yaml. > > v2->v3: > Fix formatting errors. > > v3->v4: > Fix bugs in the two yaml files. > > v4->v5: > No change. > > v5->v6: > Rewrite the two yaml files. > > v6->v7: > 1.Update compatible strings in "ingenic,cpu.yaml". > 2.Fix formatting errors, and enum for compatible strings. > 3.Remove unnecessary "ingenic,soc.yaml". > > v7->v8: > No change. > > .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > > diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > new file mode 100644 > index 00000000..afb0207 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Bindings for Ingenic XBurst family CPUs > + > +maintainers: > + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> > + > +description: > + Ingenic XBurst family CPUs shall have the following properties. > + > +properties: > + compatible: > + oneOf: > + > + - description: Ingenic XBurst®1 CPU Cores > + items: This is a single compatible string, right? If so, drop items. > + enum: > + - ingenic,xburst-mxu1.0 > + - ingenic,xburst-fpu1.0-mxu1.1 > + - ingenic,xburst-fpu2.0-mxu2.0 > + > + - description: Ingenic XBurst®2 CPU Cores > + items: > + enum: > + - ingenic,xburst2-fpu2.1-mxu2.1-smt Just: const: ingenic,xburst2-fpu2.1-mxu2.1-smt Continuing to append CPU features isn't going to scale well. Does 'xburst2' imply certain features? If so, not really any need to have them be explicit. > + > + reg: > + maxItems: 1 > + > +required: > + - device_type > + - compatible > + - reg > + > +examples: > + - | > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; > + reg = <0>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; > + reg = <1>; > + }; > + }; > +... > -- > 2.7.4 >
在 2020/5/27 上午3:29, Rob Herring 写道: > On Tue, May 19, 2020 at 10:35:21PM +0800, 周琰杰 (Zhou Yanjie) wrote: >> Document the available properties for the SoC root node and the >> CPU nodes of the devicetree for the Ingenic XBurst SoCs. >> >> Tested-by: H. Nikolaus Schaller <hns@goldelico.com> >> Tested-by: Paul Boddie <paul@boddie.org.uk> >> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> --- >> >> Notes: >> v1->v2: >> Change the two Document from txt to yaml. >> >> v2->v3: >> Fix formatting errors. >> >> v3->v4: >> Fix bugs in the two yaml files. >> >> v4->v5: >> No change. >> >> v5->v6: >> Rewrite the two yaml files. >> >> v6->v7: >> 1.Update compatible strings in "ingenic,cpu.yaml". >> 2.Fix formatting errors, and enum for compatible strings. >> 3.Remove unnecessary "ingenic,soc.yaml". >> >> v7->v8: >> No change. >> >> .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++++++++++++++++++++++ >> 1 file changed, 57 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml >> >> diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml >> new file mode 100644 >> index 00000000..afb0207 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml >> @@ -0,0 +1,57 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Bindings for Ingenic XBurst family CPUs >> + >> +maintainers: >> + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> >> + >> +description: >> + Ingenic XBurst family CPUs shall have the following properties. >> + >> +properties: >> + compatible: >> + oneOf: >> + >> + - description: Ingenic XBurst®1 CPU Cores >> + items: > This is a single compatible string, right? If so, drop items. Sure, I'll drop it. And because the SMP driver has some other work that can't be completed in a short time, so I will send this patch separately. >> + enum: >> + - ingenic,xburst-mxu1.0 >> + - ingenic,xburst-fpu1.0-mxu1.1 >> + - ingenic,xburst-fpu2.0-mxu2.0 >> + >> + - description: Ingenic XBurst®2 CPU Cores >> + items: >> + enum: >> + - ingenic,xburst2-fpu2.1-mxu2.1-smt > Just: const: ingenic,xburst2-fpu2.1-mxu2.1-smt > > Continuing to append CPU features isn't going to scale well. Does > 'xburst2' imply certain features? If so, not really any need to have > them be explicit. XBurst (XBurst1) is the first generation CPU core of Ingenic, its basic property is single-issue in-order execution, XBurst2 is the second generation CPU core of Ingenic, its basic property is daul-issue limited out-of-order execution, and both CPU cores can cooperate with some extended propeties, such as different versions of FPU, different versions of MXU instruction set, with or without simultaneous multi-threading. Currently there is only one processor entity based on XBurst2 is produced, so there is only one string for now. Thanks and best regards! >> + >> + reg: >> + maxItems: 1 >> + >> +required: >> + - device_type >> + - compatible >> + - reg >> + >> +examples: >> + - | >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; >> + reg = <0>; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; >> + reg = <1>; >> + }; >> + }; >> +... >> -- >> 2.7.4 >>
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index 00000000..afb0207 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> + +description: + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: + oneOf: + + - description: Ingenic XBurst®1 CPU Cores + items: + enum: + - ingenic,xburst-mxu1.0 + - ingenic,xburst-fpu1.0-mxu1.1 + - ingenic,xburst-fpu2.0-mxu2.0 + + - description: Ingenic XBurst®2 CPU Cores + items: + enum: + - ingenic,xburst2-fpu2.1-mxu2.1-smt + + reg: + maxItems: 1 + +required: + - device_type + - compatible + - reg + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <1>; + }; + }; +...