| Message ID | 1598255043-11839-1-git-send-email-chenhc@lemote.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 01ce6d4d2c8157b076425e3dd8319948652583c5 |
| Headers | show |
| Series | MIPS: Loongson-3: Fix fp register access if MSA enabled | expand |
Ping? On Mon, Aug 24, 2020 at 3:40 PM Huacai Chen <chenhc@lemote.com> wrote: > > If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64() > /set_fpr64() in the original unaligned instruction emulation code access > the wrong fp registers. This is because the current code doesn't specify > the correct index field, so fix it. > > Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation") > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Signed-off-by: Pei Huang <huangpei@loongson.cn> > --- > arch/mips/loongson64/cop2-ex.c | 24 ++++++++---------------- > 1 file changed, 8 insertions(+), 16 deletions(-) > > diff --git a/arch/mips/loongson64/cop2-ex.c b/arch/mips/loongson64/cop2-ex.c > index f130f62..00055d4 100644 > --- a/arch/mips/loongson64/cop2-ex.c > +++ b/arch/mips/loongson64/cop2-ex.c > @@ -95,10 +95,8 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, > if (res) > goto fault; > > - set_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lswc2_format.rt, value); > - set_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lswc2_format.rq, value_next); > + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rt], 0, value); > + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rq], 0, value_next); > compute_return_epc(regs); > own_fpu(1); > } > @@ -130,15 +128,13 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, > goto sigbus; > > lose_fpu(1); > - value_next = get_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lswc2_format.rq); > + value_next = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rq], 0); > > StoreDW(addr + 8, value_next, res); > if (res) > goto fault; > > - value = get_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lswc2_format.rt); > + value = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rt], 0); > > StoreDW(addr, value, res); > if (res) > @@ -204,8 +200,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, > if (res) > goto fault; > > - set_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lsdc2_format.rt, value); > + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0, value); > compute_return_epc(regs); > own_fpu(1); > > @@ -221,8 +216,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, > if (res) > goto fault; > > - set_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lsdc2_format.rt, value); > + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0, value); > compute_return_epc(regs); > own_fpu(1); > break; > @@ -286,8 +280,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, > goto sigbus; > > lose_fpu(1); > - value = get_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lsdc2_format.rt); > + value = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0); > > StoreW(addr, value, res); > if (res) > @@ -305,8 +298,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, > goto sigbus; > > lose_fpu(1); > - value = get_fpr64(current->thread.fpu.fpr, > - insn.loongson3_lsdc2_format.rt); > + value = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0); > > StoreDW(addr, value, res); > if (res) > -- > 2.7.0 >
On Tue, Sep 22, 2020 at 10:06:24AM +0800, Huacai Chen wrote: > On Mon, Aug 24, 2020 at 3:40 PM Huacai Chen <chenhc@lemote.com> wrote: > > > > If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64() > > /set_fpr64() in the original unaligned instruction emulation code access > > the wrong fp registers. This is because the current code doesn't specify > > the correct index field, so fix it. > > > > Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation") > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Signed-off-by: Pei Huang <huangpei@loongson.cn> > > --- > > arch/mips/loongson64/cop2-ex.c | 24 ++++++++---------------- > > 1 file changed, 8 insertions(+), 16 deletions(-) should this go via mips-fixes ? Thomas.
Hi, Thomas, On Tue, Sep 22, 2020 at 3:04 PM Thomas Bogendoerfer <tsbogend@alpha.franken.de> wrote: > > On Tue, Sep 22, 2020 at 10:06:24AM +0800, Huacai Chen wrote: > > On Mon, Aug 24, 2020 at 3:40 PM Huacai Chen <chenhc@lemote.com> wrote: > > > > > > If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64() > > > /set_fpr64() in the original unaligned instruction emulation code access > > > the wrong fp registers. This is because the current code doesn't specify > > > the correct index field, so fix it. > > > > > > Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation") > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > > Signed-off-by: Pei Huang <huangpei@loongson.cn> > > > --- > > > arch/mips/loongson64/cop2-ex.c | 24 ++++++++---------------- > > > 1 file changed, 8 insertions(+), 16 deletions(-) > > should this go via mips-fixes ? Yes, it should go. Huacai > > Thomas. > > -- > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a > good idea. [ RFC1925, 2.3 ]
On Mon, Aug 24, 2020 at 03:44:03PM +0800, Huacai Chen wrote: > If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64() > /set_fpr64() in the original unaligned instruction emulation code access > the wrong fp registers. This is because the current code doesn't specify > the correct index field, so fix it. > > Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation") > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Signed-off-by: Pei Huang <huangpei@loongson.cn> > --- > arch/mips/loongson64/cop2-ex.c | 24 ++++++++---------------- > 1 file changed, 8 insertions(+), 16 deletions(-) applied to mips-fixes. Thomas.
diff --git a/arch/mips/loongson64/cop2-ex.c b/arch/mips/loongson64/cop2-ex.c index f130f62..00055d4 100644 --- a/arch/mips/loongson64/cop2-ex.c +++ b/arch/mips/loongson64/cop2-ex.c @@ -95,10 +95,8 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, if (res) goto fault; - set_fpr64(current->thread.fpu.fpr, - insn.loongson3_lswc2_format.rt, value); - set_fpr64(current->thread.fpu.fpr, - insn.loongson3_lswc2_format.rq, value_next); + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rt], 0, value); + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rq], 0, value_next); compute_return_epc(regs); own_fpu(1); } @@ -130,15 +128,13 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, goto sigbus; lose_fpu(1); - value_next = get_fpr64(current->thread.fpu.fpr, - insn.loongson3_lswc2_format.rq); + value_next = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rq], 0); StoreDW(addr + 8, value_next, res); if (res) goto fault; - value = get_fpr64(current->thread.fpu.fpr, - insn.loongson3_lswc2_format.rt); + value = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lswc2_format.rt], 0); StoreDW(addr, value, res); if (res) @@ -204,8 +200,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, if (res) goto fault; - set_fpr64(current->thread.fpu.fpr, - insn.loongson3_lsdc2_format.rt, value); + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0, value); compute_return_epc(regs); own_fpu(1); @@ -221,8 +216,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, if (res) goto fault; - set_fpr64(current->thread.fpu.fpr, - insn.loongson3_lsdc2_format.rt, value); + set_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0, value); compute_return_epc(regs); own_fpu(1); break; @@ -286,8 +280,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, goto sigbus; lose_fpu(1); - value = get_fpr64(current->thread.fpu.fpr, - insn.loongson3_lsdc2_format.rt); + value = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0); StoreW(addr, value, res); if (res) @@ -305,8 +298,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action, goto sigbus; lose_fpu(1); - value = get_fpr64(current->thread.fpu.fpr, - insn.loongson3_lsdc2_format.rt); + value = get_fpr64(¤t->thread.fpu.fpr[insn.loongson3_lsdc2_format.rt], 0); StoreDW(addr, value, res); if (res)
If MSA is enabled, FPU_REG_WIDTH is 128 rather than 64, then get_fpr64() /set_fpr64() in the original unaligned instruction emulation code access the wrong fp registers. This is because the current code doesn't specify the correct index field, so fix it. Fixes: f83e4f9896eff614d0f2547a ("MIPS: Loongson-3: Add some unaligned instructions emulation") Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Pei Huang <huangpei@loongson.cn> --- arch/mips/loongson64/cop2-ex.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-)