| Message ID | 1599819978-13999-1-git-send-email-chenhc@lemote.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [V2,1/2] MIPS: Loongson64: Increase NR_IRQS to 320 | expand |
On Fri, 11 Sep 2020 18:26:17 +0800, Huacai Chen wrote: > Modernized Loongson64 uses a hierarchical organization for interrupt > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > is not enough to represent all interrupts, so let's increase NR_IRQS to > 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256). Applied to irq/irqchip-fixes-5.9, thanks! [2/2] irqchip/loongson-htvec: Fix initial interrupt clearing commit: 1d1e5630de78f7253ac24b92cee6427c3ff04d56 Patch 1/1 can go via the MIPS tree. Cheers, M.
On Fri, Sep 11, 2020 at 06:26:17PM +0800, Huacai Chen wrote: > Modernized Loongson64 uses a hierarchical organization for interrupt > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > is not enough to represent all interrupts, so let's increase NR_IRQS to > 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256). > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > --- > arch/mips/include/asm/mach-loongson64/irq.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) applied to mips-next. Thomas.
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..7450d45 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,8 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_MAX_CHAINED_IRQS 40 /* Chained IRQs means those not directly used by devices */ +#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256) #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256). Signed-off-by: Huacai Chen <chenhc@lemote.com> --- arch/mips/include/asm/mach-loongson64/irq.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)