From patchwork Thu Jan 24 01:09:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 10777593 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51626139A for ; Wed, 23 Jan 2019 17:04:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E6122D442 for ; Wed, 23 Jan 2019 17:04:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 82B142D45C; Wed, 23 Jan 2019 17:04:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.9 required=2.0 tests=BAYES_00,DATE_IN_FUTURE_06_12, MAILING_LIST_MULTI,RCVD_DOUBLE_IP_LOOSE,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2F652D442 for ; Wed, 23 Jan 2019 17:04:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725896AbfAWREM (ORCPT ); Wed, 23 Jan 2019 12:04:12 -0500 Received: from [182.148.157.197] ([182.148.157.197]:34588 "HELO eyou.net" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with SMTP id S1725994AbfAWREL (ORCPT ); Wed, 23 Jan 2019 12:04:11 -0500 X-EYOU-SPAMVALUE: 0 X-EMDG-ORIGINAL-FROM: X-EMDG-ORIGINAL-TO: X-EMDG-ORIGINAL-IP: 125.71.5.39 X-EMDG-VER: 4.1.1 X-EMDG-ABROAD: no Received: (eyou anti_spam gateway 4.1.0); Thu, 24 Jan 2019 01:04:38 +0800 X-EMDG-MID: <748263078.28197@eyou.net> Received: from 125.71.5.39 by 182.148.157.197 with SMTP; Thu, 24 Jan 2019 01:04:38 +0800 Received: from localhost ([127.0.0.1]) by cduestc.cn with sendmail id 649d5605120bee4f8068c59179a34600; Thu, 24 Jan 2019 09:09:13 +0800 Date: Thu, 24 Jan 2019 09:09:13 +0800 From: "Zhou Yanjie" Subject: =?utf-8?q?=5BPATCH_3/4=5D_Pinctrl=3A_Ingenic=3A_Unify_the_function_?= =?utf-8?q?name_prefix_to__=22ingenic=5Fgpio=5F=22=2E?= To: "linus.walleij" Cc: "linux-gpio" , "linux-kernel" , "linux-mips" , "paul" , "syq" , "jiaxun.yang" Message-Id: <190124090913361712002288@cduestc.edu.cn> MIME-Version: 1.0 X-Mailer: eYou WebMail 8.13.6 X-Eyou-Client: 171.221.112.138 X-Eyou-Is-Onercpt: 0 X-Eyou-Sender: Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zhou Yanjie In the original code, some function names begin with "ingenic_gpio_", and some with "gpio_ingenic_". For the sake of uniform style, all of them are changed to the beginning of "ingenic_gpio_". Signed-off-by: Zhou Yanjie --- drivers/pinctrl/pinctrl-ingenic.c | 46 +++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 6501f35..2b3f7e4 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -715,7 +715,7 @@ static const struct ingenic_chip_info jz4780_chip_info = { .pull_downs = jz4770_pull_downs, }; -static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) +static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -724,7 +724,7 @@ static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) return (u32) val; } -static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc, +static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, u8 reg, u8 offset, bool set) { if (set) @@ -738,7 +738,7 @@ static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc, static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset) { - unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN); + unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); return !!(val & BIT(offset)); } @@ -747,9 +747,9 @@ static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value) { if (jzgc->jzpc->version >= ID_JZ4770) - gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); + ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); else - gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); + ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); } static void irq_set_type(struct ingenic_gpio_chip *jzgc, @@ -767,21 +767,21 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, switch (type) { case IRQ_TYPE_EDGE_RISING: - gpio_ingenic_set_bit(jzgc, reg2, offset, true); - gpio_ingenic_set_bit(jzgc, reg1, offset, true); + ingenic_gpio_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_set_bit(jzgc, reg1, offset, true); break; case IRQ_TYPE_EDGE_FALLING: - gpio_ingenic_set_bit(jzgc, reg2, offset, false); - gpio_ingenic_set_bit(jzgc, reg1, offset, true); + ingenic_gpio_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_set_bit(jzgc, reg1, offset, true); break; case IRQ_TYPE_LEVEL_HIGH: - gpio_ingenic_set_bit(jzgc, reg2, offset, true); - gpio_ingenic_set_bit(jzgc, reg1, offset, false); + ingenic_gpio_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_set_bit(jzgc, reg1, offset, false); break; case IRQ_TYPE_LEVEL_LOW: default: - gpio_ingenic_set_bit(jzgc, reg2, offset, false); - gpio_ingenic_set_bit(jzgc, reg1, offset, false); + ingenic_gpio_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_set_bit(jzgc, reg1, offset, false); break; } } @@ -791,7 +791,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); + ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); } static void ingenic_gpio_irq_unmask(struct irq_data *irqd) @@ -799,7 +799,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); - gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); + ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); } static void ingenic_gpio_irq_enable(struct irq_data *irqd) @@ -809,9 +809,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) int irq = irqd->hwirq; if (jzgc->jzpc->version >= ID_JZ4770) - gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); + ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); else - gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); + ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); ingenic_gpio_irq_unmask(irqd); } @@ -825,9 +825,9 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) ingenic_gpio_irq_mask(irqd); if (jzgc->jzpc->version >= ID_JZ4770) - gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); + ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); else - gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); + ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); } static void ingenic_gpio_irq_ack(struct irq_data *irqd) @@ -850,9 +850,9 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) } if (jzgc->jzpc->version >= ID_JZ4770) - gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); + ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); else - gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); + ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); } static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) @@ -907,9 +907,9 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irq_chip, desc); if (jzgc->jzpc->version >= ID_JZ4770) - flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG); + flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); else - flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG); + flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); for_each_set_bit(i, &flag, 32) generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));