Message ID | 1ebc11c9588ddf0afcec336b35b50751fe1e89f8.1560024463.git.petrcvekcz@gmail.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | MIPS: lantiq: irq: Various fixes, add SMP support | expand |
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 2df5d37d0a7b..21ccd580f8f5 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -54,10 +54,6 @@ #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) -/* our 2 ipi interrupts for VSMP */ -#define MIPS_CPU_IPI_RESCHED_IRQ 0 -#define MIPS_CPU_IPI_CALL_IRQ 1 - /* we have a cascade of 8 irqs */ #define MIPS_CPU_IRQ_CASCADE 8