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[RFC,2/5] mips: ralink: add dt-binding document for rt2880-clock driver

Message ID 20190330123317.16821-3-drvlabo@gmail.com (mailing list archive)
State Superseded
Headers show
Series MIPS: ralink: peripheral clock gating driver | expand

Commit Message

NOGUCHI Hiroshi March 30, 2019, 12:33 p.m. UTC
Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 .../bindings/clock/ralink,rt2880-clock.txt    | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
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Patch

diff --git a/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
new file mode 100644
index 000000000000..6f0757046df4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
@@ -0,0 +1,20 @@ 
+* Clock bindings for Ralink/Mediatek MIPS based SoCs
+
+Required properties:
+ - compatible: must be "ralink,rt2880-clock" and
+     one of the following, to identify SoC series
+        "mediatek,mt7620-clock"   for MT7620
+        "mediatek,mt7628-clock"   for MT7628/MT7688
+        "mediatek,mt7621-clock"   for MT7621
+ - #clock-cells: must be 1
+ - ralink,sysctl: a phandle to a ralink syscon register region
+
+
+Example:
+
+clkctrl: clkctrl {
+	compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
+	#clock-cells = <1>;
+
+	ralink,sysctl = <&sysc>;
+};