[RFC,4/5] mips: ralink: mt7628: add nodes for clock provider

Commit Message

NOGUCHI Hiroshi March 30, 2019, 12:33 p.m. UTC

Signed-off-by: NOGUCHI Hiroshi <[e-mail]>
---
 arch/mips/boot/dts/ralink/mt7628a.dtsi | 37 ++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

Patch

diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8faaecc..67ce939f6b2b 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -26,6 +26,18 @@ 
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	pll: pll {
+		compatible = "mediatek,mt7620-pll", "syscon";
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
+	};
+
+	clkctrl: clkctrl {
+		compatible = "mediatek,mt7628-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+		ralink,sysctl = <&sysc>;
+	};
+
 	palmbus@10000000 {
 		compatible = "palmbus";
 		reg = <0x10000000 0x200000>;
@@ -62,10 +74,29 @@ 
 			reg = <0x300 0x100>;
 		};
 
+		spi0: spi@b00 {
+			compatible = "ralink,mt7621-spi";
+			reg = <0xb00 0x100>;
+
+			clocks = <&clkctrl 18>;
+			clock-names = "spi";
+
+			resets = <&resetc 18>;
+			reset-names = "spi";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
 		uart0: uartlite@c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&clkctrl 12>;
+			clock-names = "uart0";
+
 			resets = <&resetc 12>;
 			reset-names = "uart0";
 
@@ -79,6 +110,9 @@ 
 			compatible = "ns16550a";
 			reg = <0xd00 0x100>;
 
+			clocks = <&clkctrl 19>;
+			clock-names = "uart1";
+
 			resets = <&resetc 19>;
 			reset-names = "uart1";
 
@@ -92,6 +126,9 @@ 
 			compatible = "ns16550a";
 			reg = <0xe00 0x100>;
 
+			clocks = <&clkctrl 20>;
+			clock-names = "uart2";
+
 			resets = <&resetc 20>;
 			reset-names = "uart2";