diff mbox series

[RFC,5/5] mips: ralink: mt7620: add nodes for clock provider

Message ID 20190330123317.16821-6-drvlabo@gmail.com (mailing list archive)
State Superseded
Headers show
Series MIPS: ralink: peripheral clock gating driver | expand

Commit Message

NOGUCHI Hiroshi March 30, 2019, 12:33 p.m. UTC 
Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi | 34 +++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

Comments

Stephen Boyd April 2, 2019, 8:32 p.m. UTC | #1 
Quoting NOGUCHI Hiroshi (2019-03-30 05:33:17)
> @@ -17,6 +27,18 @@
>                 compatible = "mti,cpu-interrupt-controller";
>         };
>  
> +       pll: pll {
> +               compatible = "mediatek,mt7620-pll", "syscon";

This binding looks wrong. It's making a node per clk in DT when we
should be making nodes only for the clk controller. The use of syscon is
also a sign that things are heading in the wrong direction.

> +               #clock-cells = <1>;
> +               clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
> +       };
> +
> +       clkctrl: clkctrl {
> +               compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
> +               #clock-cells = <1>;
> +               ralink,sysctl = <&sysc>;
> +       };
diff mbox series

Patch

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 1f6e5320f486..bc56b8f9a530 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -5,11 +5,21 @@ 
 	compatible = "ralink,mtk7620a-soc";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "mips,mips24KEc";
+			device_type = "cpu";
+			reg = <0>;
 		};
 	};
 
+	resetc: reset-controller {
+		compatible = "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
 	cpuintc: cpuintc {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -17,6 +27,18 @@ 
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	pll: pll {
+		compatible = "mediatek,mt7620-pll", "syscon";
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
+	};
+
+	clkctrl: clkctrl {
+		compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+		ralink,sysctl = <&sysc>;
+	};
+
 	palmbus@10000000 {
 		compatible = "palmbus";
 		reg = <0x10000000 0x200000>;
@@ -25,8 +47,8 @@ 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,mt7620a-sysc";
+		sysc: sysc@0 {
+			compatible = "ralink,mt7620a-sysc", "syscon";
 			reg = <0x0 0x100>;
 		};
 
@@ -46,10 +68,16 @@ 
 			reg = <0x300 0x100>;
 		};
 
-		uartlite@c00 {
+		uartlite: uartlite@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&clkctrl 19>;
+			clock-names = "uartl";
+
+			resets = <&resetc 19>;
+			reset-names = "uartl";
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;