[3/4] MIPS: Sync icache for whole exception vector

Commit Message

Paul Burton April 30, 2019, 10:53 p.m. UTC

Rather than performing cache flushing for a fixed 0x400 bytes, use the
actual size of the vector in order to ensure we cover all emitted code
on systems that make use of vectored interrupts.

Signed-off-by: Paul Burton <[e-mail]>
---
 arch/mips/kernel/traps.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Philippe Mathieu-Daudé May 1, 2019, 3:09 p.m. UTC | #1

On 5/1/19 12:53 AM, Paul Burton wrote:
> Rather than performing cache flushing for a fixed 0x400 bytes, use the
> actual size of the vector in order to ensure we cover all emitted code
> on systems that make use of vectored interrupts.
> 
> Signed-off-by: Paul Burton <[e-mail]>
> ---
>  arch/mips/kernel/traps.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 9b565ed51662..2775190adbe7 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -2454,7 +2454,7 @@ void __init trap_init(void)
>  	else
>  		set_handler(0x080, &except_vec3_generic, 0x80);
>  
> -	local_flush_icache_range(ebase, ebase + 0x400);
> +	local_flush_icache_range(ebase, ebase + vec_size);
>  
>  	sort_extable(__start___dbe_table, __stop___dbe_table);
>  
> 

Reviewed-by: Philippe Mathieu-Daudé <[e-mail]>

Patch

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9b565ed51662..2775190adbe7 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2454,7 +2454,7 @@  void __init trap_init(void)
 	else
 		set_handler(0x080, &except_vec3_generic, 0x80);
 
-	local_flush_icache_range(ebase, ebase + 0x400);
+	local_flush_icache_range(ebase, ebase + vec_size);
 
 	sort_extable(__start___dbe_table, __stop___dbe_table);