diff mbox series

[2/2] MIPS: Decode config3 register on Ingenic SoCs

Message ID 20190507224357.23778-2-paul@crapouillou.net (mailing list archive)
State Accepted
Headers show
Series [1/2] MIPS: Rename JZRISC to XBURST | expand

Commit Message

Paul Cercueil May 7, 2019, 10:43 p.m. UTC 
XBurst misses a config2 register, so config3 decode was skipped in
decode_configs().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 arch/mips/kernel/cpu-probe.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Paul Burton July 22, 2019, 9:21 p.m. UTC | #1 
Hello,

Paul Cercueil wrote:
> XBurst misses a config2 register, so config3 decode was skipped in
> decode_configs().
> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>

Applied to mips-next.

Thanks,
    Paul

[ This message was auto-generated; if you believe anything is incorrect
  then please email paul.burton@mips.com to report it. ]
diff mbox series

Patch

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index fdb73c1b0cd7..ed240cdfef46 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1960,9 +1960,17 @@  static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
+
+	/*
+	 * XBurst misses a config2 register, so config3 decode was skipped in
+	 * decode_configs().
+	 */
+	decode_config3(c);
+
 	/* XBurst does not implement the CP0 counter. */
 	c->options &= ~MIPS_CPU_COUNTER;
 	BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
+
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_XBURST:
 		c->cputype = CPU_XBURST;