| Message ID | 20190604163311.19059-1-paul@crapouillou.net (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 1323c3b72a987de57141cabc44bf9cd83656bc70 |
| Headers | show |
| Series | MIPS: lb60: Fix pin mappings | expand |
On Tue, Jun 4, 2019 at 6:34 PM Paul Cercueil <paul@crapouillou.net> wrote: > The pin mappings introduced in commit 636f8ba67fb6 > ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers") > are completely wrong. The pinctrl driver name is incorrect, and the > function and group fields are swapped. > > Fixes: 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers") > Cc: <stable@vger.kernel.org> > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Such things happen. Are you planning to phase all the board files over to use devicetree eventually? Yours, Linus Walleij
Le sam. 8 juin 2019 à 0:10, Linus Walleij <linus.walleij@linaro.org> a écrit : > On Tue, Jun 4, 2019 at 6:34 PM Paul Cercueil <paul@crapouillou.net> > wrote: > >> The pin mappings introduced in commit 636f8ba67fb6 >> ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several >> drivers") >> are completely wrong. The pinctrl driver name is incorrect, and the >> function and group fields are swapped. >> >> Fixes: 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl >> configuration for several drivers") >> Cc: <stable@vger.kernel.org> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > Such things happen. Are you planning to phase all the board files over > to use devicetree eventually? Yes, that's definitely what's planned; right now the blockers are patchsets [1] and [2]. [1] is ignored by everybody because there's no maintainer for drivers/memory/. [2] is a year-long effort that still doesn't show me the light at the end of the tunnel. [1] https://lkml.org/lkml/2019/6/4/743 [2] https://lkml.org/lkml/2019/5/21/679 Cheers -Paul
On Sat, Jun 8, 2019 at 12:14 PM Paul Cercueil <paul@crapouillou.net> wrote: > Le sam. 8 juin 2019 à 0:10, Linus Walleij <linus.walleij@linaro.org> a > écrit : > > On Tue, Jun 4, 2019 at 6:34 PM Paul Cercueil <paul@crapouillou.net> > > wrote: > > > >> The pin mappings introduced in commit 636f8ba67fb6 > >> ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several > >> drivers") > >> are completely wrong. The pinctrl driver name is incorrect, and the > >> function and group fields are swapped. > >> > >> Fixes: 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl > >> configuration for several drivers") > >> Cc: <stable@vger.kernel.org> > >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> > > > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > > > Such things happen. Are you planning to phase all the board files over > > to use devicetree eventually? > > Yes, that's definitely what's planned; right now the blockers are > patchsets [1] and [2]. [1] is ignored by everybody because there's no > maintainer for drivers/memory/. [2] is a year-long effort that still > doesn't show me the light at the end of the tunnel. > > [1] https://lkml.org/lkml/2019/6/4/743 > [2] https://lkml.org/lkml/2019/5/21/679 What? That's unacceptable, the last resort is usually to send the patches to Andrew Morton (whether fair or not) when nothing gets applied. In this case I would however encourage the MIPS maintainer to simply queue this stuff in the MIPS tree as blocking his arch work if not merged, Ralf would you consider just queueing this? I do not think the other Linus would mind. Yours, Linus Walleij
Le sam. 8 juin 2019 à 15:39, Linus Walleij <linus.walleij@linaro.org> a écrit : > On Sat, Jun 8, 2019 at 12:14 PM Paul Cercueil <paul@crapouillou.net> > wrote: >> Le sam. 8 juin 2019 à 0:10, Linus Walleij >> <linus.walleij@linaro.org> a >> écrit : >> > On Tue, Jun 4, 2019 at 6:34 PM Paul Cercueil >> <paul@crapouillou.net> >> > wrote: >> > >> >> The pin mappings introduced in commit 636f8ba67fb6 >> >> ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several >> >> drivers") >> >> are completely wrong. The pinctrl driver name is incorrect, and >> the >> >> function and group fields are swapped. >> >> >> >> Fixes: 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl >> >> configuration for several drivers") >> >> Cc: <stable@vger.kernel.org> >> >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> >> > >> > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> >> > >> > Such things happen. Are you planning to phase all the board files >> over >> > to use devicetree eventually? >> >> Yes, that's definitely what's planned; right now the blockers are >> patchsets [1] and [2]. [1] is ignored by everybody because there's >> no >> maintainer for drivers/memory/. [2] is a year-long effort that still >> doesn't show me the light at the end of the tunnel. >> >> [1] https://lkml.org/lkml/2019/6/4/743 >> [2] https://lkml.org/lkml/2019/5/21/679 > > What? That's unacceptable, the last resort is usually to send the > patches to Andrew Morton (whether fair or not) when nothing gets > applied. > > In this case I would however encourage the MIPS maintainer to > simply queue this stuff in the MIPS tree as blocking his arch work > if not merged, Ralf would you consider just queueing this? > I do not think the other Linus would mind. It's not that critical - it's not blocking until [2] gets merged too. But yes, it's been sitting idle for a while. > Yours, > Linus Walleij
Hi Linus / Paul, On Sat, Jun 08, 2019 at 03:39:07PM +0200, Linus Walleij wrote: > > Yes, that's definitely what's planned; right now the blockers are > > patchsets [1] and [2]. [1] is ignored by everybody because there's no > > maintainer for drivers/memory/. [2] is a year-long effort that still > > doesn't show me the light at the end of the tunnel. > > > > [1] https://lkml.org/lkml/2019/6/4/743 > > [2] https://lkml.org/lkml/2019/5/21/679 > > What? That's unacceptable, the last resort is usually to send the > patches to Andrew Morton (whether fair or not) when nothing gets > applied. > > In this case I would however encourage the MIPS maintainer to > simply queue this stuff in the MIPS tree as blocking his arch work > if not merged, Ralf would you consider just queueing this? > I do not think the other Linus would mind. I'd be happy to queue up [1] in mips-next, it looks pretty innocuous. I can definitely feel Paul's pain on [2], but I see v12 is still getting feedback so... Thanks, Paul
Hello, Paul Cercueil wrote: > The pin mappings introduced in commit 636f8ba67fb6 > ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers") > are completely wrong. The pinctrl driver name is incorrect, and the > function and group fields are swapped. > > Fixes: 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers") > Cc: <stable@vger.kernel.org> > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Applied to mips-next. Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.burton@mips.com to report it. ]
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index 071e9d94eea7..daed44ee116d 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -466,27 +466,27 @@ static unsigned long pin_cfg_bias_disable[] = { static struct pinctrl_map pin_map[] __initdata = { /* NAND pin configuration */ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand", - "10010000.jz4740-pinctrl", "nand", "nand-cs1"), + "10010000.pin-controller", "nand-cs1", "nand"), /* fbdev pin configuration */ PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT, - "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"), + "10010000.pin-controller", "lcd-8bit", "lcd"), PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP, - "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"), + "10010000.pin-controller", "lcd-no-pins", "lcd"), /* MMC pin configuration */ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"), + "10010000.pin-controller", "mmc-1bit", "mmc"), PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"), + "10010000.pin-controller", "mmc-4bit", "mmc"), PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable), + "10010000.pin-controller", "PD0", pin_cfg_bias_disable), PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0", - "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable), + "10010000.pin-controller", "PD2", pin_cfg_bias_disable), /* PWM pin configuration */ PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm", - "10010000.jz4740-pinctrl", "pwm4", "pwm4"), + "10010000.pin-controller", "pwm4", "pwm4"), };
The pin mappings introduced in commit 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers") are completely wrong. The pinctrl driver name is incorrect, and the function and group fields are swapped. Fixes: 636f8ba67fb6 ("MIPS: JZ4740: Qi LB60: Add pinctrl configuration for several drivers") Cc: <stable@vger.kernel.org> Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- arch/mips/jz4740/board-qi_lb60.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)