From patchwork Mon Jul 15 10:15:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Rothwell X-Patchwork-Id: 11043547 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0CF113BD for ; Mon, 15 Jul 2019 10:15:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D8B65204FD for ; Mon, 15 Jul 2019 10:15:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C3BE12022C; Mon, 15 Jul 2019 10:15:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 486B82022C for ; Mon, 15 Jul 2019 10:15:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729627AbfGOKPw (ORCPT ); Mon, 15 Jul 2019 06:15:52 -0400 Received: from ozlabs.org ([203.11.71.1]:42583 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729591AbfGOKPv (ORCPT ); Mon, 15 Jul 2019 06:15:51 -0400 Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 45nKDM6h0xz9sNy; Mon, 15 Jul 2019 20:15:47 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=canb.auug.org.au; s=201702; t=1563185749; bh=jsWNP/KQzccDDDLR5oNKr0dnsNeu8nGq7K7jrvJpn2c=; h=Date:From:To:Cc:Subject:From; b=N+v3iZfz3Z3sIjJn76r2EucYfJc3BUn9wQa/iH/stkhzk4HDQyqFapUvk7e3PNNu4 B7vKTbso21HAjPNstYXhjs2vvypSJPkCseTZJR5sYcUgK+D6vaTUyWWNtGJDlAp4wO nOZguZZcs6Wzj8byWYBViOgj4KVI8GEE3F8XHMyDXlsBRW4GOUUYQ0Q6q8nR08y9bj P4mZGTRKO/y2hWz8l1/zKNn9BpEukko61F3lPHZgfOqn51B97+aE+GFSqlOwtsUgdZ NdPADPAG7CyHsi385gOVX8NQQQopbhnrFmntxlmkVT6smPmEAeBJUejAteNEAYjnq2 ApaC694bG3IdA== Date: Mon, 15 Jul 2019 20:15:40 +1000 From: Stephen Rothwell To: Ralf Baechle , Paul Burton , James Hogan Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , "Gustavo A. R. Silva" , Kees Cook , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH] MIPS: perf events: handle switch statement falling through warnings Message-ID: <20190715201540.1e4bb96a@canb.auug.org.au> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that we build with -Wimplicit-fallthrough=3, some warnings are produced in the arch/mips perf events code that are promoted to errors: arch/mips/kernel/perf_event_mipsxx.c:792:3: error: this statement may fall through [-Werror=implicit-fallthrough=] arch/mips/kernel/perf_event_mipsxx.c:795:3: error: this statement may fall through [-Werror=implicit-fallthrough=] arch/mips/kernel/perf_event_mipsxx.c:798:3: error: this statement may fall through [-Werror=implicit-fallthrough=] arch/mips/kernel/perf_event_mipsxx.c:1407:6: error: this statement may fall through [-Werror=implicit-fallthrough=] Assume the fall throughs are deliberate amd annotate/eliminate them. Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Gustavo A. R. Silva Cc: Kees Cook Signed-off-by: Stephen Rothwell --- arch/mips/kernel/perf_event_mipsxx.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) I haven't even build tested this, sorry, but will add it to linux-next tomorrow. It should be no worse than the current state :-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index e0ebaa0a333e..40106731e97e 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -790,15 +790,19 @@ static void reset_counters(void *arg) case 4: mipsxx_pmu_write_control(3, 0); mipspmu.write_counter(3, 0); + /* fall through */ case 3: mipsxx_pmu_write_control(2, 0); mipspmu.write_counter(2, 0); + /* fall through */ case 2: mipsxx_pmu_write_control(1, 0); mipspmu.write_counter(1, 0); + /* fall through */ case 1: mipsxx_pmu_write_control(0, 0); mipspmu.write_counter(0, 0); + /* fall through */ } } @@ -1379,7 +1383,7 @@ static int mipsxx_pmu_handle_shared_irq(void) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct perf_sample_data data; unsigned int counters = mipspmu.num_counters; - u64 counter; + unsigned int n; int handled = IRQ_NONE; struct pt_regs *regs; @@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void) perf_sample_data_init(&data, 0, 0); - switch (counters) { -#define HANDLE_COUNTER(n) \ - case n + 1: \ - if (test_bit(n, cpuc->used_mask)) { \ - counter = mipspmu.read_counter(n); \ - if (counter & mipspmu.overflow) { \ - handle_associated_event(cpuc, n, &data, regs); \ - handled = IRQ_HANDLED; \ - } \ + for (n = (counters > 4) ? 3 : (counters - 1); n >= 0; n--) { + u64 counter; + + if (test_bit(n, cpuc->used_mask)) { + counter = mipspmu.read_counter(n); + if (counter & mipspmu.overflow) { + handle_associated_event(cpuc, n, &data, regs); + handled = IRQ_HANDLED; + } } - HANDLE_COUNTER(3) - HANDLE_COUNTER(2) - HANDLE_COUNTER(1) - HANDLE_COUNTER(0) } #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS