| Message ID | 20190831154027.6943-1-paul.burton@mips.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 5474682934753827d61d1226ba74ea75787b923d |
| Headers | show |
| Series | [1/3] MIPS: Select R3k-style TLB in Kconfig | expand |
On 8/31/19 5:40 PM, Paul Burton wrote: > Currently areas where we need to determine whether the TLB is R3k-style > need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX. > > Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above, > allowing us to simplify checks for R3k-style TLBs by only checking for > this new Kconfig option. > > Signed-off-by: Paul Burton <paul.burton@mips.com> > --- > > arch/mips/Kconfig | 7 ++++++- > arch/mips/include/asm/pgtable-32.h | 4 ++-- > arch/mips/include/asm/pgtable-bits.h | 6 +++--- > arch/mips/include/asm/pgtable.h | 4 ++-- > arch/mips/mm/Makefile | 5 +++-- > 5 files changed, 16 insertions(+), 10 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 31c7044e34e6..3f18aa018a0c 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1575,6 +1575,7 @@ config CPU_R3000 > depends on SYS_HAS_CPU_R3000 > select CPU_HAS_WB > select CPU_HAS_LOAD_STORE_LR > + select CPU_R3K_TLB > select CPU_SUPPORTS_32BIT_KERNEL > select CPU_SUPPORTS_HIGHMEM > help > @@ -1590,6 +1591,7 @@ config CPU_TX39XX > depends on SYS_HAS_CPU_TX39XX > select CPU_SUPPORTS_32BIT_KERNEL > select CPU_HAS_LOAD_STORE_LR > + select CPU_R3K_TLB > > config CPU_VR41XX > bool "R41xx" > @@ -2280,6 +2282,9 @@ config CPU_R2300_FPU > depends on MIPS_FP_SUPPORT > default y if CPU_R3000 || CPU_TX39XX > > +config CPU_R3K_TLB > + bool > + > config CPU_R4K_FPU > bool > depends on MIPS_FP_SUPPORT > @@ -2287,7 +2292,7 @@ config CPU_R4K_FPU > > config CPU_R4K_CACHE_TLB > bool > - default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) > + default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON) > > config MIPS_MT_SMP > bool "MIPS MT SMP support (1 TC on each available VPE)" > diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h > index e600570789f4..ba967148b016 100644 > --- a/arch/mips/include/asm/pgtable-32.h > +++ b/arch/mips/include/asm/pgtable-32.h > @@ -221,7 +221,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) > ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) > #define pte_unmap(pte) ((void)(pte)) > > -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) > +#if defined(CONFIG_CPU_R3K_TLB) > > /* Swap entries must have VALID bit cleared. */ > #define __swp_type(x) (((x).val >> 10) & 0x1f) > @@ -266,6 +266,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) > > #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ > > -#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */ > +#endif /* defined(CONFIG_CPU_R3K_TLB) */ > > #endif /* _ASM_PGTABLE_32_H */ > diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h > index c2c1060b43ef..5f1ced8cba07 100644 > --- a/arch/mips/include/asm/pgtable-bits.h > +++ b/arch/mips/include/asm/pgtable-bits.h > @@ -82,7 +82,7 @@ enum pgtable_bits { > _PAGE_SPECIAL_SHIFT, > }; > > -#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) > +#elif defined(CONFIG_CPU_R3K_TLB) > > /* Page table bits used for r3k systems */ > enum pgtable_bits { > @@ -151,7 +151,7 @@ enum pgtable_bits { > #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) > #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) > #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) > -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) > +#if defined(CONFIG_CPU_R3K_TLB) > # define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) > # define _CACHE_MASK _CACHE_UNCACHED > # define _PFN_SHIFT PAGE_SHIFT > @@ -209,7 +209,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) > /* > * Cache attributes > */ > -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) > +#if defined(CONFIG_CPU_R3K_TLB) > > #define _CACHE_CACHABLE_NONCOHERENT 0 > #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED > diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h > index d60f47a9088c..4dca733d5076 100644 > --- a/arch/mips/include/asm/pgtable.h > +++ b/arch/mips/include/asm/pgtable.h > @@ -199,7 +199,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt > static inline void set_pte(pte_t *ptep, pte_t pteval) > { > *ptep = pteval; > -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) > +#if !defined(CONFIG_CPU_R3K_TLB) > if (pte_val(pteval) & _PAGE_GLOBAL) { > pte_t *buddy = ptep_buddy(ptep); > /* > @@ -218,7 +218,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) > static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) > { > htw_stop(); > -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) > +#if !defined(CONFIG_CPU_R3K_TLB) > /* Preserve global status for the pair */ > if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) > set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); > diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile > index 949d43eefda1..46f483e952c8 100644 > --- a/arch/mips/mm/Makefile > +++ b/arch/mips/mm/Makefile > @@ -28,10 +28,11 @@ obj-$(CONFIG_HIGHMEM) += highmem.o > obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o > obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o > > +obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o > obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o > -obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o > +obj-$(CONFIG_CPU_R3000) += c-r3k.o > obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o > -obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o > +obj-$(CONFIG_CPU_TX39XX) += c-tx39.o > obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o > > obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Hello, Paul Burton wrote: > Currently areas where we need to determine whether the TLB is R3k-style > need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX. > > Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above, > allowing us to simplify checks for R3k-style TLBs by only checking for > this new Kconfig option. Series applied to mips-next. > MIPS: Select R3k-style TLB in Kconfig > commit 547468293475 > https://git.kernel.org/mips/c/547468293475 > > Signed-off-by: Paul Burton <paul.burton@mips.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > MIPS: tlbex: Simplify r3k check > commit 54e8d9f07d8a > https://git.kernel.org/mips/c/54e8d9f07d8a > > Signed-off-by: Paul Burton <paul.burton@mips.com> > > MIPS: tlbex: Remove cpu_has_local_ebase > commit 775b089aeffa > https://git.kernel.org/mips/c/775b089aeffa > > Signed-off-by: Paul Burton <paul.burton@mips.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paul.burton@mips.com to report it. ]
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31c7044e34e6..3f18aa018a0c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1575,6 +1575,7 @@ config CPU_R3000 depends on SYS_HAS_CPU_R3000 select CPU_HAS_WB select CPU_HAS_LOAD_STORE_LR + select CPU_R3K_TLB select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_HIGHMEM help @@ -1590,6 +1591,7 @@ config CPU_TX39XX depends on SYS_HAS_CPU_TX39XX select CPU_SUPPORTS_32BIT_KERNEL select CPU_HAS_LOAD_STORE_LR + select CPU_R3K_TLB config CPU_VR41XX bool "R41xx" @@ -2280,6 +2282,9 @@ config CPU_R2300_FPU depends on MIPS_FP_SUPPORT default y if CPU_R3000 || CPU_TX39XX +config CPU_R3K_TLB + bool + config CPU_R4K_FPU bool depends on MIPS_FP_SUPPORT @@ -2287,7 +2292,7 @@ config CPU_R4K_FPU config CPU_R4K_CACHE_TLB bool - default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON) + default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON) config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index e600570789f4..ba967148b016 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -221,7 +221,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) #define pte_unmap(pte) ((void)(pte)) -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3K_TLB) /* Swap entries must have VALID bit cleared. */ #define __swp_type(x) (((x).val >> 10) & 0x1f) @@ -266,6 +266,6 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ -#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */ +#endif /* defined(CONFIG_CPU_R3K_TLB) */ #endif /* _ASM_PGTABLE_32_H */ diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index c2c1060b43ef..5f1ced8cba07 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -82,7 +82,7 @@ enum pgtable_bits { _PAGE_SPECIAL_SHIFT, }; -#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#elif defined(CONFIG_CPU_R3K_TLB) /* Page table bits used for r3k systems */ enum pgtable_bits { @@ -151,7 +151,7 @@ enum pgtable_bits { #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3K_TLB) # define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) # define _CACHE_MASK _CACHE_UNCACHED # define _PFN_SHIFT PAGE_SHIFT @@ -209,7 +209,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) /* * Cache attributes */ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3K_TLB) #define _CACHE_CACHABLE_NONCOHERENT 0 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index d60f47a9088c..4dca733d5076 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -199,7 +199,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt static inline void set_pte(pte_t *ptep, pte_t pteval) { *ptep = pteval; -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) +#if !defined(CONFIG_CPU_R3K_TLB) if (pte_val(pteval) & _PAGE_GLOBAL) { pte_t *buddy = ptep_buddy(ptep); /* @@ -218,7 +218,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { htw_stop(); -#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) +#if !defined(CONFIG_CPU_R3K_TLB) /* Preserve global status for the pair */ if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 949d43eefda1..46f483e952c8 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -28,10 +28,11 @@ obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o +obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o +obj-$(CONFIG_CPU_R3000) += c-r3k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o -obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o +obj-$(CONFIG_CPU_TX39XX) += c-tx39.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
Currently areas where we need to determine whether the TLB is R3k-style need to check for either of CONFIG_CPU_R3000 || CONFIG_CPU_TX39XX. Introduce a new CONFIG_CPU_R3K_TLB & select it from both of the above, allowing us to simplify checks for R3k-style TLBs by only checking for this new Kconfig option. Signed-off-by: Paul Burton <paul.burton@mips.com> --- arch/mips/Kconfig | 7 ++++++- arch/mips/include/asm/pgtable-32.h | 4 ++-- arch/mips/include/asm/pgtable-bits.h | 6 +++--- arch/mips/include/asm/pgtable.h | 4 ++-- arch/mips/mm/Makefile | 5 +++-- 5 files changed, 16 insertions(+), 10 deletions(-)