| Message ID | 20190831154027.6943-3-paul.burton@mips.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 775b089aeffa98d5f69045d9dc4fe3aaba1bc9e1 |
| Headers | show |
| Series | [1/3] MIPS: Select R3k-style TLB in Kconfig | expand |
On 8/31/19 5:40 PM, Paul Burton wrote: > The cpu_has_local_ebase macro is, confusingly, not used to indicate > whether the EBase register is local to a CPU or not. Instead it > indicates whether we want to generate the TLB refill exception vector > each time a CPU is brought online. Doing this makes little sense on any > system, since we always use the same value for EBase & thus we cannot > have different TLB refill exception handlers per CPU. > > Regenerating the code is not only pointless but also can be actively > harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only > once to avoid CPU Hotplug problem") described. That commit introduced > cpu_has_local_ebase to disable the handler regeneration for Loongson > machines, but this is by no means a Loongson-specific problem. > > Remove cpu_has_local_ebase & simply generate the TLB refill handler once > during boot, just like the rest of the TLB exception handlers. > > Signed-off-by: Paul Burton <paul.burton@mips.com> > --- > > arch/mips/include/asm/cpu-features.h | 3 --- > arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 1 - > .../include/asm/mach-loongson64/cpu-feature-overrides.h | 1 - > arch/mips/mm/tlbex.c | 9 ++------- > 4 files changed, 2 insertions(+), 12 deletions(-) > > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index 4e2bea8875f5..983a6a7f43a1 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -243,9 +243,6 @@ > #ifndef cpu_has_pindexed_dcache > #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) > #endif > -#ifndef cpu_has_local_ebase > -#define cpu_has_local_ebase 1 > -#endif > > /* > * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors > diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h > index 1c11310bc8ad..00beb69bfab9 100644 > --- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h > +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h > @@ -32,7 +32,6 @@ > #define cpu_has_vtag_icache 0 > #define cpu_has_ic_fills_f_dc 0 > #define cpu_has_pindexed_dcache 0 > -#define cpu_has_local_ebase 0 > #define cpu_icache_snoops_remote_store 1 > #define cpu_has_mips_4 0 > #define cpu_has_mips_5 0 > diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h > index 581915ce231c..4aca25f2ff06 100644 > --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h > +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h > @@ -43,7 +43,6 @@ > #define cpu_has_vint 0 > #define cpu_has_vtag_icache 0 > #define cpu_has_watch 1 > -#define cpu_has_local_ebase 0 > > #ifdef CONFIG_CPU_LOONGSON3 > #define cpu_has_wsbh 1 > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index 6e3ca9cc5249..e01cb33bfa1a 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -2609,12 +2609,9 @@ void build_tlb_refill_handler(void) > > if (cpu_has_3kex) { > #ifndef CONFIG_MIPS_PGD_C0_CONTEXT > - if (cpu_has_local_ebase) > - build_r3000_tlb_refill_handler(); > if (!run_once) { > - if (!cpu_has_local_ebase) > - build_r3000_tlb_refill_handler(); > build_setup_pgd(); > + build_r3000_tlb_refill_handler(); > build_r3000_tlb_load_handler(); > build_r3000_tlb_store_handler(); > build_r3000_tlb_modify_handler(); > @@ -2638,13 +2635,11 @@ void build_tlb_refill_handler(void) > build_r4000_tlb_modify_handler(); > if (cpu_has_ldpte) > build_loongson3_tlb_refill_handler(); > - else if (!cpu_has_local_ebase) > + else > build_r4000_tlb_refill_handler(); > flush_tlb_handlers(); > run_once++; > } > - if (cpu_has_local_ebase) > - build_r4000_tlb_refill_handler(); > if (cpu_has_xpa) > config_xpa_params(); > if (cpu_has_htw) > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Sat, 31 Aug 2019, Paul Burton wrote: > Remove cpu_has_local_ebase & simply generate the TLB refill handler once > during boot, just like the rest of the TLB exception handlers. You may want to update this comment: /* * The refill handler is generated per-CPU, multi-node systems * may have local storage for it. The other handlers are only * needed once. */ accordingly then (assuming you've checked it no longer applies before making this change). Maciej
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 4e2bea8875f5..983a6a7f43a1 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -243,9 +243,6 @@ #ifndef cpu_has_pindexed_dcache #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif -#ifndef cpu_has_local_ebase -#define cpu_has_local_ebase 1 -#endif /* * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h index 1c11310bc8ad..00beb69bfab9 100644 --- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h @@ -32,7 +32,6 @@ #define cpu_has_vtag_icache 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_pindexed_dcache 0 -#define cpu_has_local_ebase 0 #define cpu_icache_snoops_remote_store 1 #define cpu_has_mips_4 0 #define cpu_has_mips_5 0 diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index 581915ce231c..4aca25f2ff06 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -43,7 +43,6 @@ #define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -#define cpu_has_local_ebase 0 #ifdef CONFIG_CPU_LOONGSON3 #define cpu_has_wsbh 1 diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 6e3ca9cc5249..e01cb33bfa1a 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2609,12 +2609,9 @@ void build_tlb_refill_handler(void) if (cpu_has_3kex) { #ifndef CONFIG_MIPS_PGD_C0_CONTEXT - if (cpu_has_local_ebase) - build_r3000_tlb_refill_handler(); if (!run_once) { - if (!cpu_has_local_ebase) - build_r3000_tlb_refill_handler(); build_setup_pgd(); + build_r3000_tlb_refill_handler(); build_r3000_tlb_load_handler(); build_r3000_tlb_store_handler(); build_r3000_tlb_modify_handler(); @@ -2638,13 +2635,11 @@ void build_tlb_refill_handler(void) build_r4000_tlb_modify_handler(); if (cpu_has_ldpte) build_loongson3_tlb_refill_handler(); - else if (!cpu_has_local_ebase) + else build_r4000_tlb_refill_handler(); flush_tlb_handlers(); run_once++; } - if (cpu_has_local_ebase) - build_r4000_tlb_refill_handler(); if (cpu_has_xpa) config_xpa_params(); if (cpu_has_htw)
The cpu_has_local_ebase macro is, confusingly, not used to indicate whether the EBase register is local to a CPU or not. Instead it indicates whether we want to generate the TLB refill exception vector each time a CPU is brought online. Doing this makes little sense on any system, since we always use the same value for EBase & thus we cannot have different TLB refill exception handlers per CPU. Regenerating the code is not only pointless but also can be actively harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem") described. That commit introduced cpu_has_local_ebase to disable the handler regeneration for Loongson machines, but this is by no means a Loongson-specific problem. Remove cpu_has_local_ebase & simply generate the TLB refill handler once during boot, just like the rest of the TLB exception handlers. Signed-off-by: Paul Burton <paul.burton@mips.com> --- arch/mips/include/asm/cpu-features.h | 3 --- arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 1 - .../include/asm/mach-loongson64/cpu-feature-overrides.h | 1 - arch/mips/mm/tlbex.c | 9 ++------- 4 files changed, 2 insertions(+), 12 deletions(-)