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Wed, 18 Sep 2019 22:03:27 +0000 From: Paul Burton To: "linux-mips@vger.kernel.org" CC: Paul Burton , Dmitry Korotin Subject: [PATCH 1/3] MIPS: Disable pte_special() for MIPS32 with 4KiB pages & RiXi Thread-Topic: [PATCH 1/3] MIPS: Disable pte_special() for MIPS32 with 4KiB pages & RiXi Thread-Index: AQHVbmzmqHjqG429vkSh9effcziumA== Date: Wed, 18 Sep 2019 22:03:27 +0000 Message-ID: <20190918220258.29428-1-paul.burton@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MN2PR04CA0030.namprd04.prod.outlook.com (2603:10b6:208:d4::43) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.23.0 x-originating-ip: [12.246.51.142] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 69021238-503e-4b53-9599-08d73c840892 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:MWHPR2201MB1375; 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Unfortunately for MIPS32 configurations with RiXi support this pushed the number of pgprot bits to 13 (ie. _PFN_SHIFT = 13). When using 4KB pages (ie. PAGE_SHIFT = 12) this results in us shifting the most significant bit of the physical address beyond the end of the PTE, leading any mapped access to a physical address above 2GB to incorrectly access an address 2GB lower than intended. For now, disable the pte_special() support for MIPS32 configurations that use 4KB pages & support RiXi. Fixes: 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support") Signed-off-by: Paul Burton Cc: Dmitry Korotin --- arch/mips/Kconfig | 2 +- arch/mips/include/asm/pgtable-bits.h | 14 +++++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3f18aa018a0c..18163c138676 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -84,7 +84,7 @@ config MIPS select RTC_LIB select SYSCTL_EXCEPTION_TRACE select VIRT_TO_BUS - select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_PTE_SPECIAL if !(32BIT && PAGE_SIZE_4KB && CPU_HAS_RIXI) menu "Machine selection" diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 409ae01ed7be..4da79b85c179 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -52,7 +52,9 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif }; /* @@ -79,7 +81,9 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif }; #elif defined(CONFIG_CPU_R3K_TLB) @@ -92,7 +96,9 @@ enum pgtable_bits { _PAGE_WRITE_SHIFT, _PAGE_ACCESSED_SHIFT, _PAGE_MODIFIED_SHIFT, +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif /* Used by TLB hardware (placed in EntryLo) */ _PAGE_GLOBAL_SHIFT = 8, @@ -116,7 +122,9 @@ enum pgtable_bits { #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) _PAGE_HUGE_SHIFT, #endif +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) _PAGE_SPECIAL_SHIFT, +#endif /* Used by TLB hardware (placed in EntryLo*) */ #if defined(CONFIG_CPU_HAS_RIXI) @@ -139,7 +147,11 @@ enum pgtable_bits { #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) # define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #endif -#define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT) +#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL) +# define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT) +#else +# define _PAGE_SPECIAL 0 +#endif /* Used by TLB hardware (placed in EntryLo*) */ #if defined(CONFIG_XPA)