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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: yQa2z/5JeLAvGCl27NAu+IFCwhMVz8rQe8v36+UVeN8vOv07PWtQVW/FS8gZfSrB2fYqEoP/XoxcxvTNPo8uoSzrC215h3v6WxeoJU2ewx+xtaB04EnrT0BAVQ3/H6na/9TxDi+luOVkqjFUMo+gDiuxfev2QPSMDH5e0lo+JJjNb+OKN4e8UoSwCVK/R/YlNubkDoSGAkb00NdSFwckKDp/S6Oltl1KiyX6A2YzZmywM84yYV2kwAG0THTWuxugyZ3zFgOEUS8lmtmDOF6siOHZQcN6t6QJ1s5ENULZGqvf/yoC0HwhJ1WxhZ1mEIEZAmcQPVg/wlSfSrlvJmAX7QtTC5Rg4v9OYYs9ACm1oEFUOy8NieFUWrZ46VE+LQOGj4K8ETbQB2WDYn6SIqJFzcomB2wd9+RY979Ows5Mcm0= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 42737e41-2df7-4b1a-c034-08d745fb1d89 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2019 23:08:33.2538 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kipr0YbbFfFrxVM3YuijGt4gcfSX4Mfajw5nm5hvCY0A5AgpdxcCW4FZWi1TXgl0oedsRb6iZDf57U4WfJVQjg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1022 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The logical operations or & xor used in the test_and_set_bit_lock(), test_and_clear_bit() & test_and_change_bit() functions currently force the value 1< --- arch/mips/include/asm/bitops.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 34d6fe3f18d0..0b0ce0adce8f 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -261,7 +261,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, " and %2, %0, %3 \n" " .set pop \n" : "=&r" (temp), "+m" (*m), "=&r" (res) - : "r" (1UL << bit) + : "ir" (1UL << bit) : __LLSC_CLOBBER); } else { loongson_llsc_mb(); @@ -274,7 +274,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, " " __SC "%2, %1 \n" " .set pop \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) - : "r" (1UL << bit) + : "ir" (1UL << bit) : __LLSC_CLOBBER); } while (unlikely(!res)); @@ -332,7 +332,7 @@ static inline int test_and_clear_bit(unsigned long nr, " and %2, %0, %3 \n" " .set pop \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) - : "r" (1UL << bit) + : "ir" (1UL << bit) : __LLSC_CLOBBER); } else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) { loongson_llsc_mb(); @@ -358,7 +358,7 @@ static inline int test_and_clear_bit(unsigned long nr, " " __SC "%2, %1 \n" " .set pop \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) - : "r" (1UL << bit) + : "ir" (1UL << bit) : __LLSC_CLOBBER); } while (unlikely(!res)); @@ -400,7 +400,7 @@ static inline int test_and_change_bit(unsigned long nr, " and %2, %0, %3 \n" " .set pop \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) - : "r" (1UL << bit) + : "ir" (1UL << bit) : __LLSC_CLOBBER); } else { loongson_llsc_mb(); @@ -413,7 +413,7 @@ static inline int test_and_change_bit(unsigned long nr, " " __SC "\t%2, %1 \n" " .set pop \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) - : "r" (1UL << bit) + : "ir" (1UL << bit) : __LLSC_CLOBBER); } while (unlikely(!res));