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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: SfrP+nZnYz4gpBrMwLAlWVyW3i+IXquODu17ejqBVmc1L/ep8b2Bqn/DaqyXr0c2/Z9iIRBOxSed/ZvSEH5zVHO+khgBtVm3A5IeAhyJ5UMYX6Y6b7qD2e+Qms8ZptIOvVA6bLMwwNxD0GC8QNT2zhQ+E+FjgXVjOToxSzWO1zs1tPMu5f/ONZUeUkJbCOhu0gH2NODyBBgb2MGR/FGTBB0AkqJeW6CyPH+fOKOVhoKhG3aCTOXOzfqCRDqpB09QDH6ZOegGTQ/NAw/04mtkn47zfGRFgDCfZ1hNceLRtntCbtakbjQSm93IrjTgTgLzoVrcOB5FYbyEMcdtnwNp88muav5NFIrh9upv7Q45aNC2mS/iJJcrulD52WrPwbRI6uTS9Puqpl1Pbp1KwIzPP4gxIrpvGE5LVVGYaKpIMqk= MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: fa24ba13-7f02-4d32-56f4-08d746b9ca3d X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Oct 2019 21:53:27.3745 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 54EYtv8P97pQ41RHp63z20ChkRbdI6DCw4a5rohz6lbmpBk8NykOz56046eXC2fZOFdwxUZjIAXUDq/8F0pNpQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1213 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Rather than #ifdef on CONFIG_CPU_* to determine whether the ins instruction is supported we can simply check MIPS_ISA_REV to discover whether we're targeting MIPSr2 or higher. Do so in order to clean up the code. Signed-off-by: Paul Burton --- Changes in v2: None arch/mips/include/asm/bitops.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 1e5739191ddf..0f5329e32e87 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -19,6 +19,7 @@ #include /* sigh ... */ #include #include +#include #include #include #include @@ -76,8 +77,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) return; } -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) - if (__builtin_constant_p(bit) && (bit >= 16)) { + if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit) && (bit >= 16)) { loongson_llsc_mb(); do { __asm__ __volatile__( @@ -90,7 +90,6 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) } while (unlikely(!temp)); return; } -#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */ loongson_llsc_mb(); do { @@ -143,8 +142,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) return; } -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) - if (__builtin_constant_p(bit)) { + if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit)) { loongson_llsc_mb(); do { __asm__ __volatile__( @@ -157,7 +155,6 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) } while (unlikely(!temp)); return; } -#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */ loongson_llsc_mb(); do { @@ -377,8 +374,7 @@ static inline int test_and_clear_bit(unsigned long nr, : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) : "r" (1UL << bit) : __LLSC_CLOBBER); -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) - } else if (__builtin_constant_p(nr)) { + } else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) { loongson_llsc_mb(); do { __asm__ __volatile__( @@ -390,7 +386,6 @@ static inline int test_and_clear_bit(unsigned long nr, : "ir" (bit) : __LLSC_CLOBBER); } while (unlikely(!temp)); -#endif } else { loongson_llsc_mb(); do {