[07/22] mips: Add MIPS32 Release 5 support

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.

Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
  must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
  are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
  ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
  accidentally clearing LL-bit when returning from an interrupt,
  exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
  introduced, which needs to have mfhc0/mthc0 instructions available.

So due to these changes GNU GCC provides an extended instructions set
support for MIPS32 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.

So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5 bit of c->isa_level and then use cpu_has_mips32_r5
where it's appropriate.

Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>

---
Even without this patch the code contains too many patterns like:
+#if defined(CONFIG_MIPS32R2) || defined(CONFIG_MIPS32R6)
What about switching it to a simpler
+#if CONFIG_TARGET_ISA_REV >= 2 ?
Though I'd prefer this config to be named like CONFIG_CPU_MIPS_REV.
What do you think?

We also could add CPU_MIPS64_R5 config support here, but I don't think
it's necessary at the moment seeing there is no any real chip ever
produced with that arch. Right?
---
 arch/mips/Kconfig                    | 34 ++++++++++++++++++++++++----
 arch/mips/Makefile                   |  1 +
 arch/mips/include/asm/asmmacro.h     | 18 ++++++++-------
 arch/mips/include/asm/compiler.h     |  5 ++++
 arch/mips/include/asm/cpu-features.h | 20 +++++++++++-----
 arch/mips/include/asm/cpu-info.h     |  2 +-
 arch/mips/include/asm/cpu-type.h     |  6 ++++-
 arch/mips/include/asm/cpu.h          |  7 +++---
 arch/mips/include/asm/fpu.h          |  4 ++--
 arch/mips/include/asm/hazards.h      |  8 ++++---
 arch/mips/include/asm/module.h       |  2 ++
 arch/mips/include/asm/stackframe.h   |  2 +-
 arch/mips/include/asm/switch_to.h    |  8 +++----
 arch/mips/kernel/cpu-probe.c         | 12 ++++++++++
 arch/mips/kernel/entry.S             |  6 ++---
 arch/mips/kernel/proc.c              |  2 ++
 arch/mips/kernel/r4k_fpu.S           | 14 ++++++------
 arch/mips/kvm/vz.c                   |  6 ++---
 arch/mips/lib/csum_partial.S         |  6 +++--
 arch/mips/mm/c-r4k.c                 |  7 +++---
 arch/mips/mm/sc-mips.c               |  7 +++---
 21 files changed, 123 insertions(+), 54 deletions(-)

Message ID	20200306124843.472228030794@mail.baikalelectronics.ru (mailing list archive)
State	Superseded
Headers	show Return-Path: <SRS0=UYFZ=4X=vger.kernel.org=linux-mips-owner@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0A301580 for <patchwork-linux-mips@patchwork.kernel.org>; Fri, 6 Mar 2020 12:50:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1A922073B for <patchwork-linux-mips@patchwork.kernel.org>; Fri, 6 Mar 2020 12:50:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727077AbgCFMst (ORCPT <rfc822;patchwork-linux-mips@patchwork.kernel.org>); Fri, 6 Mar 2020 07:48:49 -0500 Received: from mail.baikalelectronics.com ([87.245.175.226]:35516 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726998AbgCFMst (ORCPT <rfc822;linux-mips@vger.kernel.org>); Fri, 6 Mar 2020 07:48:49 -0500 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 472228030794; Fri, 6 Mar 2020 12:48:43 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5kThnAxJGwEA; Fri, 6 Mar 2020 15:48:41 +0300 (MSK) From: <Sergey.Semin@baikalelectronics.ru> To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> CC: Serge Semin <Sergey.Semin@baikalelectronics.ru>, Serge Semin <fancer.lancer@gmail.com>, Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>, Paul Burton <paulburton@kernel.org>, Ralf Baechle <ralf@linux-mips.org>, <linux-mips@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org> Subject: [PATCH 07/22] mips: Add MIPS32 Release 5 support Date: Fri, 6 Mar 2020 15:46:50 +0300 In-Reply-To: <20200306124705.6595-1-Sergey.Semin@baikalelectronics.ru> References: <20200306124705.6595-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Message-Id: <20200306124843.472228030794@mail.baikalelectronics.ru> Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: <linux-mips.vger.kernel.org> X-Mailing-List: linux-mips@vger.kernel.org
Series	mips: Prepare MIPS-arch code for Baikal-T1 SoC support \| expand [00/22] mips: Prepare MIPS-arch code for Baikal-T1 SoC support [02/22] dt-bindings: Add MIPS CPC controller as a trivial devices [06/22] mips: cm: Add L2 ECC/parity errors reporting [07/22] mips: Add MIPS32 Release 5 support [08/22] mips: Add MIPS Warrior P5600 support [10/22] mips: Add CP0 Write Merge config support [11/22] mips: Add CONFIG/CONFIG6 reg fields macro [12/22] mips: MAAR: Use more precise address mask [13/22] mips: MAAR: Add XPA mode support [14/22] mips: early_printk_8250: Use offset-sized IO-mem accessors [15/22] mips: Use offset-sized IO-mem accessors in CPS debug printout [19/22] mips: Add udelay lpj numbers adjustment [20/22] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled [21/22] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU [v2,01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema

[07/22] mips: Add MIPS32 Release 5 support

Commit Message

Patch