| Message ID | 20200529035915.20790-2-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: dw: Add generic DW DMA controller support | expand |
Hello! On 29.05.2020 6:58, Serge Semin wrote: > Seeing DW APB SSI controller doesn't support setting the exactly > requested SPI bus frequency, but only a rounded frequency determined > by means of the odd-numbered half-worded reference clock divider, > it would be good tune the SPI core up and initialize the current ^ to? > transfer effective_speed_hz. By doing so the core will be able to > execute the xfer-related delays with better accuracy. > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Feng Tang <feng.tang@intel.com> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: linux-mips@vger.kernel.org > Cc: devicetree@vger.kernel.org [...] MBR, Sergei
On Fri, May 29, 2020 at 11:49:12AM +0300, Sergei Shtylyov wrote: > Hello! > > On 29.05.2020 6:58, Serge Semin wrote: > > > Seeing DW APB SSI controller doesn't support setting the exactly > > requested SPI bus frequency, but only a rounded frequency determined > > by means of the odd-numbered half-worded reference clock divider, > > it would be good tune the SPI core up and initialize the current > ^ to? Thanks! I'll fix it in the next patchset version. -Sergey > > > transfer effective_speed_hz. By doing so the core will be able to > > execute the xfer-related delays with better accuracy. > > > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> > > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > > Cc: Arnd Bergmann <arnd@arndb.de> > > Cc: Feng Tang <feng.tang@intel.com> > > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: linux-mips@vger.kernel.org > > Cc: devicetree@vger.kernel.org > [...] > > MBR, Sergei
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 9d6904d30104..050cb2ea0812 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -352,6 +352,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, spi_set_clk(dws, chip->clk_div); } + transfer->effective_speed_hz = dws->max_freq / chip->clk_div; dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); cr0 = dws->update_cr0(master, spi, transfer);
Seeing DW APB SSI controller doesn't support setting the exactly requested SPI bus frequency, but only a rounded frequency determined by means of the odd-numbered half-worded reference clock divider, it would be good tune the SPI core up and initialize the current transfer effective_speed_hz. By doing so the core will be able to execute the xfer-related delays with better accuracy. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org --- drivers/spi/spi-dw.c | 1 + 1 file changed, 1 insertion(+)