diff mbox series

[v2,3/3] MIPS: Loongson64: Reorder CPUCFG model match arms

Message ID 20200530073243.16411-4-git@xen0n.name (mailing list archive)
State Mainlined
Commit dd25ed7361fb543d32f0da66e1e492563e64938e
Headers show
Series CPUCFG emulation future-proofing & HWCAP addition | expand

Commit Message

WANG Xuerui May 30, 2020, 7:32 a.m. UTC 
Originally the match arms are ordered by model release date, however
the LOONGSON_64R cores are even more reduced capability-wise. So put
them at top of the switch block.

Suggested-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/mips/loongson64/cpucfg-emul.c | 32 +++++++++++++++---------------
 1 file changed, 16 insertions(+), 16 deletions(-)

Comments

Huacai Chen May 30, 2020, 10:27 a.m. UTC | #1 
Reviewed-by: Huacai Chen <chenhc@lemote.com>

On Sat, May 30, 2020 at 3:34 PM WANG Xuerui <git@xen0n.name> wrote:
>
> Originally the match arms are ordered by model release date, however
> the LOONGSON_64R cores are even more reduced capability-wise. So put
> them at top of the switch block.
>
> Suggested-by: Huacai Chen <chenhc@lemote.com>
> Signed-off-by: WANG Xuerui <git@xen0n.name>
> ---
>  arch/mips/loongson64/cpucfg-emul.c | 32 +++++++++++++++---------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
> index ca75f07252df..cd619b47ba1f 100644
> --- a/arch/mips/loongson64/cpucfg-emul.c
> +++ b/arch/mips/loongson64/cpucfg-emul.c
> @@ -137,6 +137,22 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>
>         /* Add CPUCFG features non-discoverable otherwise. */
>         switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
> +       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
> +               decode_loongson_config6(c);
> +               probe_uca(c);
> +
> +               c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
> +                       LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
> +                       LOONGSON_CFG1_TGTSYNC);
> +               c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
> +                       LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
> +                       LOONGSON_CFG2_LPM_REV2);
> +               c->loongson3_cpucfg_data[2] = 0;
> +               break;
> +
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
>                 c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
>                         LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
> @@ -164,22 +180,6 @@ void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
>                         LOONGSON_CFG3_LCAMVW_REV1);
>                 break;
>
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
> -       case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
> -               decode_loongson_config6(c);
> -               probe_uca(c);
> -
> -               c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
> -                       LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
> -                       LOONGSON_CFG1_TGTSYNC);
> -               c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
> -                       LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
> -                       LOONGSON_CFG2_LPM_REV2);
> -               c->loongson3_cpucfg_data[2] = 0;
> -               break;
> -
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
>         case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0:
> --
> 2.26.2
>
diff mbox series

Patch

diff --git a/arch/mips/loongson64/cpucfg-emul.c b/arch/mips/loongson64/cpucfg-emul.c
index ca75f07252df..cd619b47ba1f 100644
--- a/arch/mips/loongson64/cpucfg-emul.c
+++ b/arch/mips/loongson64/cpucfg-emul.c
@@ -137,6 +137,22 @@  void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 
 	/* Add CPUCFG features non-discoverable otherwise. */
 	switch (c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) {
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
+	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
+		decode_loongson_config6(c);
+		probe_uca(c);
+
+		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
+			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
+			LOONGSON_CFG1_TGTSYNC);
+		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
+			LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
+			LOONGSON_CFG2_LPM_REV2);
+		c->loongson3_cpucfg_data[2] = 0;
+		break;
+
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R1:
 		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
 			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LSUCA |
@@ -164,22 +180,6 @@  void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)
 			LOONGSON_CFG3_LCAMVW_REV1);
 		break;
 
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_0:
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_1:
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_2:
-	case PRID_IMP_LOONGSON_64R | PRID_REV_LOONGSON2K_R1_3:
-		decode_loongson_config6(c);
-		probe_uca(c);
-
-		c->loongson3_cpucfg_data[0] |= (LOONGSON_CFG1_LSLDR0 |
-			LOONGSON_CFG1_LSSYNCI | LOONGSON_CFG1_LLSYNC |
-			LOONGSON_CFG1_TGTSYNC);
-		c->loongson3_cpucfg_data[1] |= (LOONGSON_CFG2_LBT1 |
-			LOONGSON_CFG2_LBT2 | LOONGSON_CFG2_LPMP |
-			LOONGSON_CFG2_LPM_REV2);
-		c->loongson3_cpucfg_data[2] = 0;
-		break;
-
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0:
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_1:
 	case PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R3_0: