| Message ID | 20200617105042.3824116-10-noltari@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 |
| Headers | show |
| Series | bmips: add bcm6345 reset controller support | expand |
On Wed, 17 Jun 2020 12:50:41 +0200, Álvaro Fernández Rojas wrote: > BCM6318 SoCs have a reset controller for certain components. > > Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> > Acked-by: Florian Fainelli <F.fainelli@gmail.com> > --- > v7: no changes. > v6: fix BCM6318_RST_HOSTMIPS value (12 vs 11). > v5: no changes. > v4: no changes. > v3: add new path with BCM6318 reset controller definitions. > > include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 include/dt-bindings/reset/bcm6318-reset.h > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h new file mode 100644 index 000000000000..f882662505ea --- /dev/null +++ b/include/dt-bindings/reset/bcm6318-reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6318_H +#define __DT_BINDINGS_RESET_BCM6318_H + +#define BCM6318_RST_SPI 0 +#define BCM6318_RST_EPHY 1 +#define BCM6318_RST_SAR 2 +#define BCM6318_RST_ENETSW 3 +#define BCM6318_RST_USBD 4 +#define BCM6318_RST_USBH 5 +#define BCM6318_RST_PCIE_CORE 6 +#define BCM6318_RST_PCIE 7 +#define BCM6318_RST_PCIE_EXT 8 +#define BCM6318_RST_PCIE_HARD 9 +#define BCM6318_RST_ADSL 10 +#define BCM6318_RST_PHYMIPS 11 +#define BCM6318_RST_HOSTMIPS 12 + +#endif /* __DT_BINDINGS_RESET_BCM6318_H */